MLCC
High Reliability IECQ-CECC Ranges
IECQ-CECC MLCC Capacitors
Electrical Details
Capacitance Range
Temperature Coefficient of
Capacitance (TCC)
C0G/NP0
X7R
C0G/NP0
X7R
Insulation Resistance (IR)
Dielectric Withstand Voltage (DWV)
C0G/NP0
X7R
0.47pF to 6.8µF
0 ± 30ppm/˚C
±15% from -55˚C to +125˚C
Cr > 50pF
≤0.0015
Cr
≤
50pF = 0.0015(15÷Cr+0.7)
≤
0.025
100G or 1000secs (whichever is the less)
Voltage applied for 5 ±1 seconds, 50mA
charging current maximum
Zero
<2% per time decade
A range of specialist high reliability MLCCs for use in
critical or high reliability environments. All fully
tested/approved and available with a range of suitable
termination options, including tin/lead plating and Syfer
FlexiCap™.
Dissipation Factor
Ageing Rate
IECQ-CECC – maximum capacitance values
0603
16V
C0G/NP0
X7R
C0G/NP0
X7R
C0G/NP0
X7R
C0G/NP0
X7R
C0G/NP0
X7R
C0G/NP0
X7R
C0G/NP0
X7R
1.5nF
100nF
1.0nF
56nF
470pF
47nF
330pF
10nF
100pF
5.6nF
n/a
n/a
n/a
n/a
0805
6.8nF
330nF
4.7nF
220nF
2.7nF
220nF
1.8nF
47nF
680pF
27nF
330pF
8.2nF
n/a
n/a
1206
22nF
1.0μF
15nF
820nF
10nF
470nF
6.8nF
150nF
2.2nF
100nF
1.5nF
33nF
470pF
4.7nF
1210
33nF
1.5μF
22nF
1.2μF
18nF
1.0μF
12nF
470nF
4.7nF
220nF
3.3nF
100nF
1.0nF
15nF
1808
33nF
1.5μF
27nF
1.2μF
18nF
680nF
12nF
330nF
4.7nF
180nF
3.3nF
100nF
1.2nF
18nF
1812
100nF
3.3μF
68nF
2.2μF
33nF
1.5μF
27nF
1.0μF
12nF
470nF
10nF
270nF
3.3nF
56nF
2220
150nF
5.6μF
100nF
4.7μF
68nF
2.2μF
47nF
1.5μF
22nF
1.0μF
15nF
560nF
8.2nF
120nF
2225
220nF
6.8μF
150nF
5.6μF
100nF
3.3μF
68nF
1.5μF
27nF
1.0μF
22nF
820nF
10nF
150nF
25V
50/63V
100V
200/250V
500V
1kV
Ordering Information – IECQ-CECC Range
1210
Chip Size
0603
0805
1206
1210
1808
1812
2220
2225
Y
Termination
Y
= FlexiCap™
termination base with
nickel barrier (100%
matte tin plating).
RoHS compliant.
H
= FlexiCap™
termination base with
nickel barrier (Tin/
lead plating with min.
10% lead). Not RoHS
compliant.
F
= Silver Palladium.
RoHS compliant.
J
= Silver base with
nickel barrier (100%
matte tin plating).
RoHS compliant.
A
= Silver base with
nickel barrier (Tin/lead
plating with min. 10%
lead). Not RoHS
compliant.
100
Rated Voltage
016
= 16V
025
= 25V
050
= 50V
063
= 63V
100
= 100V
200
= 200V
250
= 250V
500
= 500V
1K0
= 1kV
0103
Capacitance in Pico
farads (pF)
First digit is 0.
Second and third digits are
significant figures of
capacitance code. The fourth
digit is number of zeros
following. Example:
0103
= 10nF
J
Capacitance
Tolerance
<10pF
B
= ±0.1pF
C
= ±0.25pF
D
= ±0.5pF
≥
10pF
F
= ±1%
G
= ±2%
J
= ±5%
K
= ±10%
M
= ±20%
D
Dielectric
Codes
D
= X7R (2R1) with
IECQCECC release
F
= C0G/NP0
(1B/NP0) with
IECQCECC release
B
= 2X1/BX
released in
accordance with
IECQ-CECC
R
= 2C1/BZ
released in
accordance with
IECQ-CECC
For
B
and
R
codes
please refer to
TCC/VCC range for
full capacitance
values
T
Packaging
T
= 178mm
(7”) reel
R
= 330mm
(13”) reel
B
= Bulk pack
- tubs or trays
___
Suffix code
Used for specific
customer
requirements
© Knowles 2014
IECQ-CECCDatasheet Issue 4 (P109796) Release Date 04/11/14
Page 1 of 9
Tel: +44 1603 723300 | Email SyferSales@knowles.com | www.knowlescapacitors.com/syfer
Soldering Information
Syfer MLCCs are compatible with all recognised
soldering/mounting methods for chip capacitors. A detailed
application note is available at syfer.com
Reflow Soldering
Syfer recommend reflow soldering as the preferred method for
mounting MLCCs. Syfer MLCCs can be reflow soldered using a
reflow profile generally defined in IPC/FEDEC J-STD-020. Sn
plated termination chip capacitors are compatible with both
conventional and lead free soldering with peak temperatures of
260 to 270˚C acceptable.
The heating ramp rate should be such that components see a
temperature rise of 1.5 to 4˚C per second to maintain
temperature uniformity through the MLCC.
The time for which the solder is molten should be maintained
at a minimum, so as to prevent solder leaching. Extended
times above 230˚C can cause problems with oxidation of Sn
plating. Use of an inert atmosphere can help if this problem is
encountered. Palladium/Silver (Pd/Ag) terminations can be
particularly susceptible to leaching with free lead, tin rich
solders and trials are recommended for this combination.
Cooling to ambient temperature should be allowed to occur
naturally, particularly if larger chip sizes are being soldered.
Natural cooling allows a gradual relaxation of thermal
mismatch stresses in the solder joints. Forced cooling should
be avoided as this can induce thermal breakage.
Wave Soldering
Wave soldering is generally acceptable, but the thermal
stresses caused by the wave have been shown to lead to
potential problems with larger or thicker chips. Particular care
should be taken when soldering SM chips larger than size 1210
and with a thickness greater than 1.0mm for this reason.
Maximum permissible wave temperature is 270˚C for SM
chips.
The total immersion time in solder should be kept to a
minimum. It is strongly recommended that Sn/Ni plated
terminations are specified for wave soldering applications.
Solder Leaching
Leaching is the term for the dissolution of silver into the solder
causing a failure of the termination system which causes
increased ESR, tan
δ
and open circuit faults, including
ultimately the possibility of the chip becoming detached.
Leaching occurs more readily with higher temperature solders
and solders with a high tin content. Pb free solders can be very
prone to leaching certain termination systems. To prevent
leaching, exercise care when choosing solder allows and
minimize both maximum temperature and dwell time with the
molten solder.
Plated terminations with nickel or copper anti-leaching barrier
layers are available in a range of top coat finishes to prevent
leaching occurring. These finishes also include Syfer FlexiCap
TM
for improved stress resistance post soldering.
Multilayer ceramic chip with nickel or copper barrier
termi
natio
n
Rework of Chip Capacitors
Syfer recommend hot air/gas as the preferred method of
applying heat for rework. Apply even heat surrounding the
component to minimise internal thermal gradients. Soldering
irons or other techniques that apply direct heat to the chip or
surrounding area should not be used as these can result in
micro cracks being generated.
Minimise the rework heat duration and allow components to
cool naturally after soldering.
Use of Silver Loaded Epoxy Adhesives
Chip capacitors can be mounted to circuit boards using silver
loaded adhesive provided the termination material of the
capacitor is selected to be compatible with the adhesive. This
is normally PdAg. Standard tin finishes are often not
recommended for use with silver loaded epoxies as there can
be electrical and mechanical issues with the joint integrity due
to material mismatch.
Handling & Storage
Components should never be handled with fingers;
perspiration and skin oils can inhibit solderability and will
aggravate cleaning.
Chip capacitors should never be handled with metallic
instruments. Metal tweezers should never be used as these
can chip the product and leave abraded metal tracks on the
product surface. Plastic or plastic coated metal types are
readily available and recommended – these should be used
with an absolute minimum of applied pressure.
Incorrect storage can lead to problems for the user. Rapid
tarnishing of the terminations, with an associated degradation
of solderability, will occur if the product comes into contact
with industrial gases such as sulphur dioxide and chlorine.
Storage in free air, particularly moist or polluted air, can result
in termination oxidation.
Packaging should not be opened until the MLCs are required
for use. If opened, the pack should be re-sealed as soon as
practicable. Alternatively, the contents could be kept in a
sealed container with an environmental control agent.
Long term storage conditions, ideally, should be temperature
controlled between -5 and +40˚C and humidity controlled
between 40% and 60% R.H.
Taped product should be stored out of direct sunlight, which
might promote deterioration in tape or adhesive performance.
Product, stored under the conditions recommended above, in
its “as received” packaging, has a minimum shelf life of 2
years.
SM Pad Design
Syfer conventional 2-terminal chip capacitors can generally be
mounted using pad designs in accordance with IPC-7351,
Generic Requirements for Surface Mount Design and Land
Pattern Standards, but there are some other factors that have
been shown to reduce mechanical stress, such as reducing the
pad width to less than the chip width. In addition, the position
of the chip on the board should also be considered.
3-terminal components are not specifically covered by IPC-
7351, but recommended pad dimensions are included in the
Syfer catalogue/website for these components.
© Knowles 2014
IECQ-CECCDatasheet Issue 4 (P109796) Release Date 04/11/14
Page 2 of 9
Tel: +44 1603 723300 | Email SyferSales@knowles.com | www.knowlescapacitors.com/syfer
FlexiCap
TM
Termination
FlexiCap
TM
has been developed as a result of listening to
customer’s experiences of stress damage to MLCCs from many
manufacturers, often caused by variations in production
processes.
Our answer is a proprietary flexible epoxy polymer termination
material that is applied to the device under the usual nickel
barrier finish. FlexiCap
TM
will accommodate a greater degree of
board bending than conventional capacitors.
REACH (Registration, Evaluation, Authorisation and
restriction of Chemicals) Statement
The main purpose of REACH is to improve the protection of
human health and the environment from the risks arising from
the use of chemicals.
Syfer Technology Ltd maintains both ISO 14001,
Environmental Management System and OHSAS 18001 Health
& Safety Management System approvals that require and
ensure compliance with corresponding legislation such as
REACH.
For further information, please contact the sales office at
SyferSales@knowles.com
Ranges are available with FlexiCap
TM
termination material
offering increased reliability and superior mechanical
performance (board flex and temperature cycling) when
compared with standard termination materials. Refer to Syfer
application note reference AN0001. FlexiCap
TM
capacitors
enable the board to be bent almost twice as much as before
mechanical cracking occurs. Refer to application note AN0002.
FlexiCap
TM
is also suitable for space applications having passed
thermal vacuum outgassing tests. Refer to Syfer application
note reference AN0026.
RoHS Compliance
Syfer routinely monitors world wide material restrictions (e.g.,
EU/China and Korea RoHS mandates) and is actively involved
in shaping future legislation.
All standard C0G/NPO, X7R, X5R and High Q Syfer MLCC
products are compliant with the EU RoHS directive (see below
for special exemptions) and those with plated terminations are
suitable for soldering common lead free solder alloys (refer to
‘Soldering Information’ for more details on soldering
limitations). Compliance with EU RoHS directive automatically
signifies compliance with some other legislation (e.g., Korea
RoHS). Please refer to the Sales Office for details of
compliance with other materials legislation.
Breakdown of material content, SGS analysis reports and tin
whisker test results are available on request.
Most Syfer MLCC components are available with non-RoHS
compliant tin/lead (SnPb) Solderable termination finish for
exempt applications and where pure tin is not acceptable.
Other tin free termination finishes may also be available –
please refer to the Sales Office for further details.
X8R ranges <250Vdc are not RoHS 2011/65/EU compliant.
Syfer has delivered millions of FlexiCap
TM
components and
during that time has collected substantial test and reliability
data, working in partnership with customers world wide, to
eliminate mechanical cracking.
An additional benefit of FlexiCap
TM
is that MLCCs can withstand
temperature cycling from -55 to 125˚C in excess of 1,000
times without cracking.
FlexiCap
TM
termination has no adverse effect on any electrical
parameters, nor affects the operation of the MLCC in any way.
Application Notes
FlexiCap
TM
may be handled, stored and transported in the
same manner as standard terminated capacitors. The
requirements for mounting and soldering FlexiCap
TM
are the
same as for standard SMD capacitors.
For customers currently using standard terminated capacitors
there should be requirement to change the assembly process
when converting to FlexiCap
TM
.
Based upon the board bend tests in accordance with IEC
60384-1 the amount of board bending required to
mechanically crack a FlexiCap
TM
terminated capacitor is
significantly increased compared with standard terminated
capacitors.
Product: X7R
Standard
Termination
FlexiCap
TM
Typical bend performance under
AEC-Q200 test conditions
2mm to 3mm
Typically 8mm to 10mm
Check the website, www.knowlescapacitors.com/syfer for
latest RoHS update.
Export Controls and Dual-use Regulations
Certain Syfer catalogue components are defined as ‘dual-use’
items under international export controls – those that can be
used for civil and military purposes which meet certain
specified technical standards.
The defining criteria for a dual-use component with respect to
Syfer products is one with a voltage rating of >750V and a
capacitance value >250nF and a series inductance <10nH.
Components defined as ‘dual-use’ under the above criteria
automatically require a licence for export outside the EU, and
may require a licence for export with the EU.
The application for a licence is routine, but customers for these
products will be asked to supply further information.
Please refer to the sales office if you require any further
information on export restrictions.
Other special components may additionally need to comply
with export regulations.
© Knowles 2014
IECQ-CECCDatasheet Issue 4 (P109796) Release Date 04/11/14
Page 3 of 9
Tel: +44 1603 723300 | Email SyferSales@knowles.com | www.knowlescapacitors.com/syfer
Ageing of Ceramic Capacitors
Capacitor ageing is a term used to describe the negative,
logarithmic capacitance change which takes place in ceramic
capacitors with time. The crystalline structure for barium
titanate based ceramics changes on passing through its Curie
temperature (known as the Curie Point) at about 125ºC. The
domain structure relaxes with time and in doing so, the
dielectric constant reduces logarithmically; this is known as the
ageing mechanism of the dielectric constant. The more stable
dielectrics have the lowest ageing rates.
The ageing process is reversible and repeatable. Whenever the
capacitor is heated to a temperature above the Curie Point the
ageing process starts again from zero.
The ageing constant, or ageing rate, is defined as the
percentage loss of capacitance due to the ageing process of
the dielectric which occurs during a decade of time (a tenfold
increase in age) and is expressed as percent per logarithmic
decade of hours. As the law of decrease of capacitance is
logarithmic, this means that for a capacitor with an ageing rate
of 1% per decade of time, the capacitance will decrease at a
rate of:
a)
b)
c)
d)
e)
1% between 1 and 10 hours
An additional 1% between the following 10 and 100
hours
An additional 1% between the following 100 and 1000
hours
An additional 1% between the following 1000 and
10000 hours
The ageing rate continues in this manner throughout
the capacitor’s life.
Tight Tolerance
One of the advantages of Syfer’s unique ‘wet process’ of
manufacture is the ability to offer capacitors with exceptionally
tight capacitance tolerances.
The accuracy of the printing screens used in the fully
automated, computer controlled manufacturing process allows
for tolerance as close as ± 1% on C0G/NP0 parts greater than
or equal to 10pF. For capacitance value less than 4.7pF
tolerances can be as tight as ± 0.05pF.
Periodic Tests Conducted and Reliability Data
For standard surface mount capacitors components are
randomly selected on a sample basis and the following routine
tests conducted:
Load Test. 1,000 hours @ 125˚C (150˚C for X8R).
Applied voltage depends on components tested
Humidity Test. 168 hours @ 85˚C/85%RH
Board Deflection (bend test)
Test results are available on request.
Conversion Factors
From
FITs
FITs
To
MTBF (hours)
MTBF (years)
Operation
10
9
÷ FITs
10
9
÷ (FITs × 8760)
FIT = Failures In Time. 1 FIT = 1 failure in 10
9
hours
MTBF = Mean Time Between Failure
Typical values of the ageing constant for our MLCCs are
Dielectric Class
Ultra Stable C0G/NP0
Stable X7R
Typical Values
Example of FIT Data Available
Negligible capacitance loss
through ageing
<2% per decade of time
Capacitance Measurements
Because of ageing it is necessary to specify an age for
reference measurements at which the capacitance shall be
within the prescribed tolerance. This is fixed at 1000 hours,
since for all practical purposes there is not much further loss of
capacitance after this time.
All capacitors shipped are within their specified tolerance at the
standard reference age of 1000 hours after having cooled
through their Curie temperature.
The ageing curve for any ceramic dielectric is a straight line
when plotted on semi-log paper.
Capacitance vs. Time
(Ageing X7R @ 1% per decade)
Component type:
Testing Location:
Results based on:
0805 (C0G/NP0 and X7R)
Syfer reliability test department
16,622,000 component test hours
© Knowles 2014
IECQ-CECCDatasheet Issue 4 (P109796) Release Date 04/11/14
Page 4 of 9
Tel: +44 1603 723300 | Email SyferSales@knowles.com | www.knowlescapacitors.com/syfer
© Knowles 2014
IECQ-CECCDatasheet Issue 4 (P109796) Release Date 04/11/14
Page 5 of 9
Tel: +44 1603 723300 | Email SyferSales@knowles.com | www.knowlescapacitors.com/syfer
Microcontroller MCU
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