YSS902
AC3D
Dolby Digital (AC-3) / Pro Logic decoder + Sub DSP
INTRODUCTION
The YSS902 is one chip LSI consisting of two built-in DSP’s ; Dolby Digital (AC-3) / Pro Logic (Main DSP) and a
sound processing DSP (Sub DSP). Sub DSP is capable of realizing various sound fields, such as virtual surround, by
down-loading the program and coefficient.
FEATURERS
Dolby Digital 5.1 channel full decode.
24 bit DSP. (Group-A Dolby Digital decoder)
No external memory is required. (Memory for center and surround channel delay is included)
Possible to decode multi-language encoded data. (possible to decode based on data-stream-number)
AC-3 karaoke mode.
Original compression mode as well as four compression modes recommended by Dolby.
Dolby Digital decoding latency is fixed to two audio blocks (512 samples).
Included de-emphasis filter.
Pro Logic decoding for Dolby Digital 2 channels decoded signal as well as ordinary PCM.
High performance 25 MIPS programmable DSP suitable for a variety of sound field processing such as original
surround, filtering, virtual surround etc.
Up to 1.36 second delay time is capable when used with an external 1Mbit SRAM. (at fs= 48 kHz)
Reads Dolby Digital decode information through the microprocessor interface.
Provide total sixteen I/O ports.
Possible to connect most of SPDIF receivers, A/D and D/A converters, by setting I/O data interface format.
Has a built-in PLL oscillation circuit to generates its own operating clock.
Internal operating clock is 25MHz.
Supply Voltage: 3.3v for core logic. 5v for I/Os.
Power saving mode.
Si-gate CMOS process.
100 QFP.(YSS902-F)
Note: "AC-3" and "Pro Logic" are registered trademarks of Dolby Laboratories Licensing Corporation.
Use of this LSI must be licensed by Dolby Laboratories Licensing Corporation.
YAMAHA CORPORATION
YSS902CATALOG
CATALOG No.:LSI-4SS902A3
1998. 7
YSS902
PIN CONFIGURATION
2
YSS902
PIN FUNCTION
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
Name
VDD1
RAMCEN
RAMA16
RAMA15
SDIB0
SDIB1
SDIB2
XI
XO
VSS
AVDD
TEST
TEST
TEST
OVFB
TEST
TEST
TEST
CPO
AVSS
VDD2
SDOA2
SDOA1
SDOA0
RAMA14
RAMA13
RAMA12
RAMA11
RAMA10
VSS
VDD1
OPORT0
OPORT1
OPORT2
OPORT3
OPORT4
OPORT5
OPORT6
OPORT7
VSS
VDD2
RAMA9
RAMA8
RAMA7
SDOB2
SDOB1
SDOB0
SDBCK1
SDWCK1
VSS
VDD2
NONPCM
CRC
MUTE
KARAOKE
I/O
-
O
O
O
I+
I+
I+
I
O
-
-
FUNCTION
+5V power supply (for I/Os)
External SRAM interface /CE
External SRAM interface address 16
External SRAM interface address 15
PCM input 0 to Sub DSP
PCM input 1 to Sub DSP
PCM input 2 to Sub DSP
Crystal oscillator connection (6.125MHz - 50.0MHz)
Crystal oscillator connection
Ground
+3.3 V power supply (for PLL circuit)
Test terminal (to be open in normal use)
Test terminal (to be open in normal use)
Test terminal (to be open in normal use)
Detection of overflow at Sub DSP
Test terminal (to be open in normal use)
Test terminal (to be open in normal use)
Test terminal (to be open in normal use)
Output terminal for PLL, to be connected to ground through the external analog filter circuit
Ground (for PLL circuit)
+3.3 V power supply (for core logic)
PCM output from Main DSP (C, LFE)
PCM output from Main DSP (LS, RS )
PCM output from Main DSP (L, R)
External SRAM interface address 14
External SRAM interface address 13
External SRAM interface address 12
External SRAM interface address 11
External SRAM interface address 10
Ground
+5V power supply (for I/Os)
Output port for general purpose
Output port for general purpose
Output port for general purpose
Output port for general purpose
Output port for general purpose
Output port for general purpose
Output port for general purpose
Output port for general purpose
Ground
+3.3 V power supply (for core logic)
External SRAM interface address 9
External SRAM interface address 8
External SRAM interface address 7
PCM output from Sub DSP
PCM output from Sub DSP
PCM output from Sub DSP
Bit clock input for SDOA, SDIB, SDOB
Word clock input for SDOA, SDIB, SDOB
Ground
+3.3 V power supply (for core logic)
Detection of non-PCM data
Detection of CRC error
Detection of auto mute
Detection of AC-3 karaoke data
3
O
A
-
-
O
O
O
O
O
O
O
O
-
-
O
O
O
O
O
O
O
O
-
-
O
O
O
O
O
O
I+
I+
-
-
O
O
O
O
YSS902
No.
Name
56 SURENC
57 /SDBCK0
58
RAMA6
59
RAMA5
60
VSS
61
RAMA4
62
/IC
63
TEST
64
RAMA3
65
/CSB
66
/CS
67
SO
68
SI
69
SCK
70
RAMA2
71
VDD1
72
RAMD0
73
RAMD1
74
RAMD2
75
RAMD3
76
RAMD4
77
RAMD5
78
RAMD6
79
RAMD7
80
VSS
81
VDD2
82 SDWCK0
83
SDBCK0
84
SDIA0
85
SDIA1
86
RAMA1
87
RAMA0
88 RAMWEN
89 RAMOEN
90
VSS
91
VDD2
92
IPORT7
93
IPORT6
94
IPORT5
95
IPORT4
96
IPORT3
97
IPORT2
98
IPORT1
99
IPORT0
100
VSS
NOTE) Is:
I+:
O:
Ot:
A:
I/O
O
O
O
O
-
O
Is
O
Is+
Is
Ot
Is
Is
O
-
I+/ O
I+/ O
I+/ O
I+/ O
I+/ O
I+/ O
I+/ O
I+/ O
-
-
I
I
I
I
O
O
O
O
-
-
I+
I+
I+
I+
I+
I+
I+
I+
-
FUNCTION
Detection of AC-3 2/0 mode Dolby surround encoded input
Inverted SDBCK0 clock output (refer to Block diagram)
External SRAM interface address 6
External SRAM interface address 5
Ground
External SRAM interface address 4
Initial clear
Test terminal (to be open in normal use)
External SRAM interface address 3
Sub DSP Chip select
Microprocessor interface Chip select input
Microprocessor interface Serial data output
Microprocessor interface / Sub DSP Serial data input
Microprocessor interface / Sub DSP clock input
External SRAM interface address 2
+5V power supply (for I/Os)
External SRAM interface data (STREAM0 output when External SRAM is not in use)
External SRAM interface data (STREAM1 output when External SRAM is not in use)
External SRAM interface data (STREAM2 output when External SRAM is not in use)
External SRAM interface data (STREAM3 output when External SRAM is not in use)
External SRAM interface data (STREAM4 output when External SRAM is not in use)
External SRAM interface data (STREAM5 output when External SRAM is not in use)
External SRAM interface data (STREAM6 output when External SRAM is not in use)
External SRAM interface data (STREAM7 output when External SRAM is not in use)
Ground
+3.3 V power supply (for core logic)
Word clock input for SDIA, SDOA, SDIB, SDOB
Bit clock input for SDIA, SDOA, SDIB, SDOB
AC-3 bitstream (or PCM) data input for Main DSP
AC-3 bitstream (or PCM) data input for Main DSP
External SRAM interface address 1
External SRAM interface address 0
External SRAM interface /WE
External SRAM interface /OE
Ground
+3.3 V power supply (for core logic)
Input port for general purpose
Input port for general purpose
Input port for general purpose
Input port for general purpose
Input port for general purpose
Input port for general purpose
Input port for general purpose
Input port for general purpose
Ground
Schmidt trigger input terminal
Input terminal with a pull-up resistor
Digital output terminal
Tri-state digital output terminal
Analog terminal
4
SO
SI
OPORT0 - 7
SCK
/CS
YSS902
BLOCK DIAGRAM
Control signals
Control signals
IPORT0 - 7
/CSB
SCK
SI
Microprocessor
Interface
Coefficient/
Program RAM
Control Registers
/SDBCK0
SDBCK1
SDWCK1
SDBCK0
SDWCK0
SDOACKSEL
L, R
SDIBCKSEL
SDOBCKSEL
SDOB0
SDIA0
LS, RS
decoder
24 * 16
Sub DSP
SDOB1
24 * 24
Main DSP
SDIB Interface
Input Buffer
AC-3/Pro Logic
SDOB Interface
SDOA Interface
SDIA Interface
SDIASEL
SDIBSEL
C, LFE
SDIA1
SDOB2
STREAM0
-
7
External RAM
interface
Data RAM
Delay RAM
ERAMUSE
CRC
Operating clock
SURENC
KARAOKE
MUTE
CRC
NONPCM
(25MHz)
PLL
XI
XO
CPO
SDIB2
SDIB1
SDIB0
RAMD0
-
7
OVFB
RAMA0
-
16
RAMOEN
RAMWEN
RAMCEN
SDOA2
SDOA1
SDOA0
5
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