Si552
P
R E L I M I N A R Y
D
A TA
S
H E E T
D
U A L
F
R E Q U E N C Y
VCXO (10 M H
Z T O
1.4 GH
Z
)
Features
Available with any-rate output
frequencies from 10 to 945 MHz and
selected frequencies to 1.4 GHz
Two selectable output frequencies
Industry-standard 7x5 mm package
Available CMOS, LVPECL, LVDS &
CML outputs
3x better frequency stability than
SAW-based oscillators
3rd generation DSPLL with
superior jitter performance
Internal fixed crystal frequency
ensures high reliability and low
aging
Lead-free/RoHS-compliant
®
Si5602
Applications
SONET / SDH
xDSL
10 GbE LAN / WAN
Low jitter clock generation
Optical Modules
Test and Measurement
Ordering Information:
See page 7.
Description
The Si552 dual frequency VCXO utilizes Silicon Laboratories advanced
DSPLL
®
circuitry to provide a very low jitter clock for all output frequencies.
The Si552 is available with any-rate output frequency from 10 to 945 MHz
and selected frequencies to 1400 MHz. Unlike traditional VCXO’s where a
different crystal is required for each output frequency, the Si552 uses one
fixed crystal frequency to provide a wide range of output frequencies. This
IC based approach allows the crystal resonator to be optimized for superior
frequency stability and reliability. In addition, DSPLL clock synthesis
provides superior supply noise rejection, simplifying the task of generating
low jitter clocks in noisy environments often found in communication
systems. The Si552 IC based VCXO is factory configurable for a wide
variety of user specifications including frequency, supply voltage and output
format. Specific configurations are factory programmed into the Si552 at
time of shipment, thereby eliminating the long lead times associated with
custom oscillators.
Functional Block Diagram
V
DD
CLK- CLK+
Fixed
Frequency XO
Any-rate
10–1400 MHz
DSPLL™
Clock Synthesis
ADC
V
C
FS
GND
Preliminary Rev. 0.2 8/05
Copyright © 2005 by Silicon Laboratories
Si552
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si552
1. Electrical Specifications
Table 1. Si552 Electrical Specifications
Parameter
Min
Typ
Max
Units
Notes
Frequency
Nominal Frequency
LVDS/CML/LVPECL
CMOS
Initial Accuracy
Temperature Stability
10
10
–1.5
–20
–50
–100
–5
–10
—
—
—
—
—
—
±1
±5
945
160
1.5
+20
+50
+100
+5
+10
Specified at time of order by P/N.
Also available in bands from
970 to 1134 MHz and 1213 to
1417 MHz.
Measured at +25 °C at time of ship-
ping and at V
C
= V
DD
/2.
Selectable option by P/N. See
Section 4. "Ordering Information" on
page 7. Measured at V
C
= V
DD
/2.
BSL determined from deviation from
best straight line fit with V
C
ranging
from 10 to 90% of V
DD
. Incremental
slope determined with V
C
ranging
from 10 to 90% of V
DD
.
Positive slope; selectable option by
P/N. See Section 4. "Ordering Infor-
mation" on page 7.
MHz
ppm
ppm
Linearity
BSL
Incremental
%
Tuning Slope (kV) from 10 to
90% of V
DD
Modulation Bandwidth
V
C
Input Impedance
Absolute Pull Range (APR)
Aging
—
—
—
—
500
—
—
180
90
45
10
—
See Notes
—
—
—
—
—
—
—
±10
Outputs
ppm/V
kHz
kΩ
—
ppm
See Section 4. "Ordering Information"
on page 7.
Projected frequency drift over 15 year
life.
Symmetry
RMS Jitter for F
OUT
> 500 MHz
Kv = 180 ppm/V
12 kHz to 20 MHz
50 kHz to 80 MHz
Kv = 45, 90 ppm/V
12 kHz to 20 MHz
50 kHz to 80 MHz
45
—
55
%
LVPECL:
LVDS:
CMOS:
V
DD
– 1.3 V (differential)
1.25 V (differential)
V
DD
/2
—
—
0.42
0.34
—
—
ps
F
OUT
> 500 MHz
Differential Modes:
LVPECL/LVDS/CML
—
—
0.28
0.31
—
—
2
Preliminary Rev. 0.2
Si552
Table 3. Environmental Conditions
Parameter
Operating Temperature
Mechanical Shock
Mechanical Vibration
Solderability
Gross & Fine Leak
Resistance to Solvents
Conditions/ Test Method
–40 to +85 °C
MIL-STD-883F, Method 2002.3 B
MIL-STD-883F, Method 2007.3 A
MIL-STD-883F, Method 203.8
MIL-STD-883F, Method 1014.7
MIL-STD-883F, Method 2016
Table 4. Pinout
Pin
1
2
3
4
5
6
Symbol
Vc
FS
Gnd
Output
Coutput
(N/A for CMOS)
V
DD
Function
Control Voltage
Frequency Select
Ground
Oscillator Output
Complementary Output
(N/C for CMOS)
Power Suppy Voltage
4
Preliminary Rev. 0.2
FPGA/CPLD
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