PI6C10810
1.2V-2.5V, 250MHz, 1:10 Networking Clock Buffer
Features
• High-speed, low-noise, non-inverting split 1-10 buffer
• Maximum Frequency up to 250 MHz
• Low output skew < 60ps (Bank A, 2.5V)
• Low duty cycle distortion < 200ps
• Low propagation delay < 2.0ns (2.5V)
• Choice of 1.2V, 1.5V, 1.8V or 2.5V supply voltage on Bank A,
Bank B, Bank C
• Industrial temperature range: –40°C
to 85°C
• Packages (Pb-free & Green): 20-pin, TSSOP (L20)
20-pin, SSOP (H20)
20-pin, QSOP (Q20)
Description
The PI6C10810 is a 1.2V to 2.5V high-speed, low-noise
1-10 non-inverting clock buffer. The key goal in designing the
PI6C10810 is to target networking applications that require low-
skew, low-jitter, and high-frequency clock distribution.
Providing output-to-output skew as low as 60ps, the PI6C10810
is an ideal clock distribution device for synchronous systems.
Designing synchronous networking systems requires a tight level
of skew from a large number of outputs.
CLK0-4 operate from V
DDA
supply.
CLK5-6 operate from V
DDC
supply.
CLK7-9 operate from V
DDB
supply.
Block Diagram
V
DDA
CLK0
Pin Configuration
BUF_IN
CLK1
BUF_IN
CLK2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDDB
CLK9
CLK8
GND
CLK7
VDDC
CLK6
GND
CLK5
CLK4
GND
CLK0
VDDA
CLK1
GND
CLK2
VDDA
CLK3
CLK4
CLK5
CLK3
GND
CLK6
CLK7
Pin Description
Pin Name
BUF_IN
CLK [0:9]
GND
V
DDA
, V
DDB
, V
DDC
Description
Input
Outputs
Ground
Power (1.2V, 1.5V, 1.8V, 2.5V)
CLK8
CLK9
V
DDC
V
DDB
11-0015
1
PS9014A
02/23/11
PI6C10810
1.2V-2.5V, 250MHz, 1:10 Networking Clock Buffer
2.5V Absolute Maximum Ratings
(Above which the useful life may
be impaired. For user guidelines only, not tested.)
Note:
Stresses greater than those listed under MAXI-
MUM RATINGS may cause permanent damage to the
V
DD
Voltage
..........................................................................–0.5V to +3.6V
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
Output Voltage (max. 3.6V)
.......................................... –0.5V to V
DD
+0.5V
indicated in the operational sections of this specification is
Input Voltage (max 3.6V)
.............................................. –0.5V to V
DD
+0.5V
not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
Storage Temperature
...........................................................–65°C to +150°C
2.5V DC Characteristics
(Over Operating Range: V
DDA,
V
DDB,
V
DDC
= 2.5V ± 0.2V, T
A
= -40° to 85°C)
Parameters Description
V
DD
V
IH
V
IL
I
I
V
OH
Supply Voltage
Input HIGH Voltage
Input LOW Voltage
Input Current
Output High Voltage
Logic HIGH level
Logic LOW level
V
DD
= Max, Vin = V
DD
or GND
V
DD
= Min., V
IN
= V
IH
or V
IL
I pin
I
OH
= -1mA
I
OH
= -2mA
I
OH
= -8mA
I
OL
= 1mA
V
OL
Output LOW Voltage
V
DD
= Min., V
IN
- V
IH
or V
IL
I
OL
= 2mA
I
OL
= 8mA
2.0
1.7
1.7
Test Conditions
(1)
Min.
2.3
1.7
-0.3
2.5
Typ.
(2)
Max.
2.7
3.6
0.7
15
Units
V
µA
0.1
0.2
0.2
V
Notes:
1. For Max. or Min. conditions, use appropriate operating range values.
2. Typical values are at V
DD
= 2.5V, +25°C ambient and maximum loading.
2.5V AC Characteristics
(Over Operating Range: V
DDA,
V
DDB,
V
DDC
= 2.5V ± 0.2V, T
A
= -40° to 85°C)
Parameters Description
t
PLH,
t
PHL
(2)
Propagation Delay BUF_IN to CLKn
t
SK(O)(3)
(3)
Test Conditions
(1)
Min.
0
1.0
–60
–30
Typ
1.5
Max.
250
2.0
60
30
150
Units
MHz
F
IN
Input Frequency
Output to Output Skew
between any two outputs
of the same device @
same transition
Bank A (CLK0 - CLK4)
Bank C (CLK5 - CLK6)
Bank B (CLK7 - CLK9)
R
L
= 500-Ohm, C
L
=
3pF, 125 MHz Out-
puts are measured @
V
DD
/2
–150
100
t
SK(P)
Pulse Skew between opposite transitions
(t
PHL
-t
PLH
) of the same output
Part to Part Skew between two identical outputs of dif-
ferent parts on the same board
(4)
Duty Cycle In @ Ins edge rate
Duty Cycle Out
Additive Jitter
Output Rise Time 20%-80% CLKn
Output Fall Time 80%-20% CLKn
200
300
ps
t
SK(T)(3)(5)
t
dc_in
t
dc_out
t
j
(5)
t
R(O)
t
F(O)
45
40
R
L
= 500-Ohm, C
L
=
3pF
0.5
0.5
55
57.5
50
0.7
0.7
%
ps
ns
Notes:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew measured at worst case temperature (max. temp).
4. Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade.
5. Guaranteed by design.
11-0015
2
PS9014A
02/23/11
PI6C10810
1.2V-2.5V, 250MHz, 1:10 Networking Clock Buffer
1.8V Absolute Maximum Ratings
(Above which the useful life may
be impaired. For user guidelines only, not tested.)
Storage Temperature
...........................................................–65°C to +150°C
V
DD
Voltage
..........................................................................–0.5V to +2.5V
Output Voltage (max 2.5V)
.......................................... –0.5V to V
DD
+0.5V
Input Voltage (max 2.5V)
............................................. –0.5V to V
DD
+0.5V
Note:
Stresses greater than those listed under MAXI-
MUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
1.8V DC Characteristics
(Over Operating Range: V
DDA
, V
DDB
, V
DDC
= 1.8V ± 0.15V, T
A
= -40° to 85°C)
Parameters
V
DD
V
IH
V
IL
I
I
V
OH
V
OL
Description
Supply Voltage
Input HIGH Voltage
Input LOW Voltage
Input Current
(3)
Output High Voltage
Output LOW Voltage
Logic HIGH level
Logic LOW level
V
DD
= Max,
Vin = V
DD
or GND
V
DD
= Min., V
IN
= V
IH
or V
IL
V
DD
= Min., V
IN
- V
IH
or V
IL
I pin
I
OH
= -2mA
I
OH
= -8mA
I
OL
= 2mA
I
OL
= 8mA
1.35
1.2
0.1
0.2
V
Test Conditions
(1)
Min.
1.65
1.1
-0.3
Typ.
(2)
1.8
Max.
1.95
2.7
0.35*V
DD
15
V
µA
Units
Notes:
1. For Max. or Min. conditions, use appropriate operating V
DD
and Ta values.
2. Typical values are at V
DD
= 1.8V, +25°C ambient and maximum loading.
3. This parameter is determined by device characterization but is not production tested.
1.8V AC Characteristics
(Over Operating Range: V
DDA
, V
DDB
, V
DDC
= 1.8V ± 0.15V, T
A
= -40° to 85°C)
Parameters Description
t
PLH,
t
PHL
(2)
Propagation Delay BUF_IN to CLKn
t
SK(O)(3)
Output to Output
Bank A (CLK0 - CLK4)
Skew between any
Bank C (CLK5 - CLK6)
two outputs of the
same device @ same
Bank B (CLK7 - CLK9)
transition
Pulse Skew between opposite transitions
(t
PHL
-t
PLH
) of the same output
Part to Part Skew between two identical outputs
of different parts on the same board
(4)
Duty Cycle In @ 1 ns edge rate
Duty Cycle Out
Additive Jitter
Output Rise Time 20% - 80% CLKn
Output Fall Time 80% - 20% CLKn
0.5
0.5
F
IN
Input Frequency
Test Conditions
(1)
Min.
0
1.0
–60
30
C
L
= 3pF, R
L
=
500-Ohm, 125 MHz
Outputs are measured
@ V
DD
/2
–200
100
2.3
Typ
Max.
200
2.8
60
30
200
200
300
45
40
55
57.5
50
0.8
0.8
%
ps
ns
ps
Units
MHz
t
SK(P)(3)
t
SK(T)(3)(5)
t
dc_in
t
dc_out
t
j
(5)
t
R(o)
t
F(o)
Notes:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew measured at worst case temperature (max. temp).
4. Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade.
5. Guaranteed by design.
11-0015
3
PS9014A
02/23/11
PI6C10810
1.2V-2.5V, 250MHz, 1:10 Networking Clock Buffer
1.5V Absolute Maximum Ratings
(Above which the useful life may
be impaired. For user guidelines only, not tested.)
Note:
Stresses greater than those listed under MAXI-
MUM RATINGS may cause permanent damage to the
V
DD
Voltage
..........................................................................–0.5V to +3.6V
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
Output Voltage (max. 3.6V)
.......................................... –0.5V to V
DD
+0.5V
indicated in the operational sections of this specification is
Input Voltage (max 3.6V)
.............................................. –0.5V to V
DD
+0.5V
not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
Storage Temperature
...........................................................–65°C to +150°C
1.5V DC Characteristics
(Over Operating Range: V
DDA,
V
DDB,
V
DDC
= 1.5V ± 0.1V, T
A
= -40° to 85°C)
Parameters Description
V
DD
V
IH
V
IL
I
I
V
OH
V
OL
Supply Voltage
Input HIGH Voltage
Input LOW Voltage
Input Current
Output High Voltage
Output LOW Voltage
Logic HIGH level
Logic LOW level
V
DD
= Max, Vin = V
DD
or GND
V
DD
= Min., V
IN
= V
IH
or V
IL
V
DD
= Min., V
IN
- V
IH
or V
IL
I pin
I
OH
= -2mA
I
OH
= -8mA
I
OL
= 2mA
I
OL
= 8mA
1.05
1.75
Test Conditions
(1)
Min.
1.4
0.65×V
DD
-0.3
1.5
Typ.
(2)
Max.
1.6
V
DD
0.35×V
DD
15
Units
V
µA
0.35
0.65
V
Notes:
1. For Max. or Min. conditions, use appropriate operating range values.
2. Typical values are at V
DD
= 1.5V, +25°C ambient and maximum loading.
1.5V AC Characteristics
(Over Operating Range: V
DDA
, V
DDB
, V
DDC
= 1.5V ± 0.1V, T
A
= -40° to 85°C)
Parameters Description
F
IN
t
R
/t
F
Input Frequency
CLKn Rise/Fall Time
Output to Output Skew Bank A (CLK0 - CLK4)
between any two outputs Bank C (CLK5 - CLK6)
of the same device @
Bank B (CLK7 - CLK9)
same transition
Pulse Skew between opposite transitions
(t
PHL
-t
PLH
) of the same output
Part to Part Skew between two identical outputs of
different parts on the same board
(4)
Duty Cycle In @ Ins edge rate
Duty Cycle Out
Additive Jitter
Output Rise Time 20% - 80% CLKn
Output Fall Time 80% - 20% CLKn
0.6
0.6
20% to 80%
2.0
–100
–50
C
L
= 3pF,
R
L
= 500-Ohms, 125
MHz Outputs are
measured @ V
DD
/2
–200
100
2.8
Test Conditions
(1)
Min.
0
Typ
Max.
200
1.0
3.5
100
50
200
200
300
45
40
55
60
50
0.9
0.9
%
ps
ns
ps
Units
MHz
ns
ns
t
PLH,
t
PHL
(2)
Propagation Delay BUF_IN to CLKn
t
SK(O)(3)
t
SK(P)(3)
t
SK(T)(3)(5)
t
dc_out
(5)
t
j
t
R(o)
t
F(o)
t
dc_in
Notes:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew measured at worst case temperature (max. temp).
4. Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade.
5. Guaranteed by design.
11-0015
4
PS9014A
02/23/11
PI6C10810
1.2V-2.5V, 250MHz, 1:10 Networking Clock Buffer
1.2V Absolute Maximum Ratings
(Above which the useful life may
be impaired. For user guidelines only, not tested.)
Note:
Stresses greater than those listed under MAXI-
MUM RATINGS may cause permanent damage to the
V
DD
Voltage
..........................................................................–0.5V to +3.6V
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
Output Voltage (max. 3.6V)
.......................................... –0.5V to V
DD
+0.5V
indicated in the operational sections of this specification is
Input Voltage (max 3.6V)
.............................................. –0.5V to V
DD
+0.5V
not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
Storage Temperature
...........................................................–65°C to +150°C
1.2V DC Characteristics
(Over Operating Range: V
DDA,
V
DDB,
V
DDC
= 1.2V ± 0.1V, T
A
= -40° to 85°C)
Parameters Description
V
DD
V
IH
V
IL
I
I
V
OH
V
OL
Supply Voltage
Input HIGH Voltage
Input LOW Voltage
Input Current
Output High Voltage
Output LOW Voltage
Logic HIGH level
Logic LOW level
V
DD
= Max, Vin = V
DD
or
GND
V
DD
= Min., V
IN
= V
IH
or V
IL
V
DD
= Min., V
IN
- V
IH
or V
IL
I pin
I
OH
= -2mA
I
OH
= -8mA
I
OL
= 2mA
I
OL
= 8mA
1.05
1.75
0.35
0.65
V
Test Conditions
(1)
Min.
1.1
0.65×V
DD
-0.3
Typ.
(2)
1.2
Max.
1.3
V
DD
+0.3
0.35×V
DD
15
V
µA
Units
Notes:
1. For Max. or Min. conditions, use appropriate operating range values.
2. Typical values are at V
DD
= 1.2V, +25°C ambient and maximum loading.
1.2V AC Characteristics
(Over Operating Range: V
DDA
, V
DDB
, V
DDC
= 1.2V ± 0.1V, T
A
= -40° to 85°C)
Parameters Description
t
PLH,
t
PHL
(2)
Propagation Delay BUF_IN to CLKn
t
SK(O)(3)
Output to Output
Skew between any
two outputs of the
same device @ same
transition
Bank A (CLK0 - CLK4)
Bank C (CLK5 - CLK6)
Bank B (CLK7 - CLK9)
C
L
= 3pF, R
L
=
500-Ohm, 125 MHz
Outputs are measured
@ V
DD
/2
F
IN
Input Frequency
Test Conditions
(1)
Min.
0
4
–150
–50
–300
200
5
Typ
Max.
150
6
150
50
300
300
300
45
40
0.9
0.9
55
60
50
1
1
%
ps
ns
ps
Units
MHz
ns
t
SK(P)(3)
t
SK(T)(3)(5)
t
DC_IN
t
DC_OUT
t
j
(5)
t
R(o)
t
F(o)
Pulse Skew between opposite transitions
(t
PHL
-t
PLH
) of the same output
Part to Part Skew between two identical outputs
of different parts on the same board
(4)
Duty Cycle In @ 1ns edge rate
Duty Cycle Out
Additive Jitter
Output Rise Time 20% - 80% CLKn
Output Fall Time 80% - 20% CLKn
Notes:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew measured at worst case temperature (max. temp).
4. Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade.
5. Guaranteed by design.
11-0015
5
PS9014A
02/23/11
京公网安备 11010802033920号
EEWORLD
