COMPANY CONFIDENTIAL
PI3VDP1431
PI3VDP1413A
Low Power Dual-mode DisplayPort 3.4Gb/s Level Shifter/Redriver
Features
ÎÎ
Dual-mode DisplayPort level shifter/Redriver
ÎÎ
Operation up to 3.4 Gbps per lane (340MHz pixel clock)
ÎÎ
Ultra HD, 3D video formats (1080p, 1080i, 720p), 48-bit
4K
Application
ÎÎ
Notebook and Desktop computers
per pixel Deep Color support
mode
Device Information
Part Number
PI3VDP1431
PI3VDP1431A
Package/Body Size Description
TQFN(32) 3x6mm
TQFN(32) 3x6mm
DDC Switch
DDC Buffer
ÎÎ
Low standby current with DDC passive Switch or Buffer
ÎÎ
Flexible 3 steps equalization control steps: 2.5, 5, 7.5 dB
ÎÎ
Pre-emphasis control 3 steps: 0, 1.5, 2.5 dB
ÎÎ
Automatic output squelch and HPD function for power
Note:
Please refer ordering addendum at the end of the datasheet
saving states management at no input signal condition
ÎÎ
Convert low-swing DC
or AC coupled differential input
ÎÎ
Integrated DDC level shifter or DDC Buffer (A version)
ÎÎ
Signal Input channels with pull-down termination resistor
ÎÎ
3.3V single power supply
ÎÎ
Pin-to-Pin compatible with PI3HDMI511/PI3HDX511A
ÎÎ
Integrated ESD protection on I/O pins. +4k/-8kV contact
ÎÎ
32-pin TQFN(ZLS32) 3x6mm package
Pin Configuration
HPD_SINK
SDA_SINK
OEB
GND
GND
Description
PI3VDP1431 is a low power dual-mode DisplayPort Level
Shifter with intergrated 3.4Gbps redriver to improve jitter
performance. Input channels has as pull-down termination
resistors(RT), optimized for displayport level shifter applica-
tion.
For mobile platforms, extended battery hours have been one
of the most demanding features. This product supports output
squelch and/or HPD detection for smart power management to
extend battery life with < 1mA stand-by current.
The device converts AC and DC coupled input signals to the
compliant signals in the HDMI or dual-mode DisplayPort
source systems. Programmable TMDS input signal equaliza-
tion helps to solve the compliance jitter issues, creating in the
non-standard HDMI source system with robust ESD/EOS
protection.
VDD
CEXT
IN_D2-
1
2
3
32 31 30 29 28
27
SCL_SINK
26 OUT_D2-
25 OUT_D2+
24 OUT_D1-
IN_D2+ 4
IN_D1- 5
IN_D1+ 6
IN_D0-
IN_D0+
IN_CLK-
7
8
9
TQFN- 32
3x6mm
23
22
21
20
19
18
17
OUT_D1+
VDD
OUT_D0-
OUT_D0+
OUT_CLK-
OUT_CLK+
EQ_S0
IN_CLK+ 10
HPD_SRC 11
12 13 14 15 16
SDA_SRC
SCL_SRC
GND
ROUT_S0
OC_S0
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15-0014
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www.pericom.com
04/14/15
COMPANY CONFIDENTIAL
PI3VDP1431, PI3VDP1431A
Low Power Dual-mode DisplayPort 3.4Gb/s Level Shifter/Redriver
Application diagram
Dual-mode
Displayort
Source System
Level Shifter
HDMI Sink
System
HDMI
Connector
Block diagram
VDD
CEXT
HPD_SRC
LDO
HPD Control
Block
HPD_SINK
VDD
ROUT
Data/Clock
Channels
Equalizer
HPD Detect
RT
GND
OEB
Control Logic
ROUT_S0
OC_S0
EQ_S0
SCL_SINK
SDA_SINK
SCL_SRC
SDA_SRC
DDC Switch/Bu er*
*PI3VDP1431 set as DDC Switch, and PI3VDP1431A set as DDC Bu er
All trademarks are property of their respective owners.
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04/14/15
COMPANY CONFIDENTIAL
PI3VDP1431, PI3VDP1431A
Low Power Dual-mode DisplayPort 3.4Gb/s Level Shifter/Redriver
Pin Description
Pin #
1,22
2
14,31,32
29
11
3
4
5
6
7
8
9
10
26
25
24
23
21
20
19
18
13
12
27
28
16
17
30
15
Pin Name
VDD
CEXT
GND
HPD_SINK
HPD_SRC
IN_D2-
IN_D2+
IN_D1-
IN_D1+
IN_D0-
IN_D0+
IN_CLK-
In_CLK+
OUT_D2-
OUT_D2+
OUT_D1-
OUT_D1+
OUT_D0-
OUT_D0+
OUT_CLK-
OUT_CLK+
SCL_SRC
SDA_SRC
SCL_SINK
SDA_SINK
OC_S0
EQ_S0
OEB
ROUT_S0
Type
PWR
PWR
GND
I
O
Description
3.3V power supply.
Add external 0.1uF capacitor to GND
LDO output for internal core supplier.
Add external capacitor (2.2uF-4.7uF) to GND
Ground connection
Sink side hot plug detector input; internal pull-down at 120 Kohm.
HPD output to source side
I
TMDS inputs. RT=50Ohm
O
TMDS outputs. ROUT=50Ohm is active when ROUT_S0 = "1"
IO
IO
IO
IO
I
I
I
I
Source side DDC Clock
Source side DDC Data
Sink side DDC Clock for connector
Sink side DDC Data for connector
TMDS output three-level pre-emphasis selection. See OC_S0 truth table. GND=0dB,
NC=1.5dB, VDD=2.5dB;
TMDS input three-level equalization selection. See EQ_S0 truth table. GND=2.5dB,
NC=5dB, VDD=7.5dB;
Output Enable control. Active low. Internal pull-down at 100 Kohm.
TMDS output double termination selection. Internally pull-up to VDD.
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04/14/15
COMPANY CONFIDENTIAL
PI3VDP1431, PI3VDP1431A
Low Power Dual-mode DisplayPort 3.4Gb/s Level Shifter/Redriver
Functional Description
Squelch Function:
Automatic output squelch function disables TMDS output when no Input signal presents. Output Disable (Squelch) Mode uses
TMDS Clock channel signal detection. When low voltage levels on the TMDS input clock signals are detected, Squelch state enables
and TMDS output port signals shall disable; when the TMDS clock input signal levels are above a pre-determined threshold voltage,
output ports shall return to the normal voltage swing levels.
HPD_SINK Shut Down
When HPD_SINK pin is floating or tie to GND, TMDS outputs shall shut down to sleep mode; HPD_SINK does not control DDC
channel.
Pre-emphasis Control OC_S0 Truth Table
Output pre-emphasis setting
ROUT_S0
"0"
OC_S0
"0"
"NC" or VDD/2
"1"
"0"
"1"
"NC" or VDD/2
"1"
Functional Description
Single-end Vswing
500 mV
500 mV
500 mV
500 mV
500 mV
500 mV
Pre-emphasis
0 dB
1.5 dB
2.5 dB
0 dB
1.5 dB
2.5 dB
Notes
Open drain output.
Open drain output: default
Open drain output
Double termination
Double termination: default
Double termination
Input Equalization EQ _S0Truth Table
EQ_S0
"0"
"NC" or VDD/2
"1"
Functional Description
2.5 dB
5 dB
7.5 dB
Note
TMDS Clock(CLK) channel EQ is always fixed as
3dB without pre-emphasis.
Output Signal Enable OEB Truth Table
OEB
"0"
"1"
Functional Description
Normal mode
Disable output signal for power saving mode
All trademarks are property of their respective owners.
15-0014
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04/14/15
COMPANY CONFIDENTIAL
PI3VDP1431, PI3VDP1431A
Low Power Dual-mode DisplayPort 3.4Gb/s Level Shifter/Redriver
Sink side Hot Plug Detect HPD_SINK Truth Table
HPD_SINK
"1"
"0"
Functional Description
Normal mode
Disable output signal for power saving mode
Source side HPD_SRC Block Diagram
300kohm Weak
Pull-down
HPD
Output
Buffer
From HPD_sink
Note:
*1: Open drain buffer is recommended with external pull-up resistor to <4.5V power supply.
All trademarks are property of their respective owners.
15-0014
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04/14/15
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