L6180
L6181
OCTAL LINE RECEIVER
ADVANCE DATA
OCTAL LINE RECEIVER FOR:
- EIA STD
RS232D
RS423A
RS422A
- CCIT
V.10
V.11
V.28
X.26
NO EXTERNAL COMPONENTS
INPUT FAIL SAFING CAPABILITY
HIGH CROSSTALK REJECTION
L6180 DATA RATE < 100KBIT/S
L6181 DATA RATE < 1MBIT/S
50V EOS OUTPUT PROTECTION
DESCRIPTION
L6180/1 is an octal line receiver in a plastic DIP
or PLCC designed to meet a wide range of digital
communications requirements as outlined in the
EIA standards RS232A without additional compo-
nents, as well as the low speed applications of
RS422A.
BLOCK DIAGRAM
DIP 28
PLCC 28
ORDERING NUMBER:
L6180A DIP 28
L6180D PLCC28
L6181A DIP 28
L6181D PLCC28
The receiver meets the CCIT recommendations
V.10, V.11, X.26 and V.28 low speed applications
(below 100KBS).
A low pass filter on the input starts to roll off at a
frequency of 100KHz.
October 1993
1/10
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
L6180 - L6181
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
DD
V
SS
C
RR
V
ID
P
tot
I
OS
t
T
op
T
stg
Supply Voltage
Supply Voltage
Logic Supply Voltage
Common Mode Range
Differential Input Voltage
Power Dissipation (PLCC 28)
Power Dissipation (DIP 28)
Output Sink Current
Output Short Circuit Time
Operating Free Air Temperature Range
Storage Temperature Range
ESD
Input Transient Protection
Parameter
Value
7
13.5
-13.5
±15
±25
800
1200
50
1
0 to 70
-65 to 150
2KV max ESD 50µJ
50V min EOS 100µs
Unit
V
V
V
V
V
mW
mW
mA
sec
°C
°C
PIN CONNECTIONS
(Top views)
DIP28
PLCC28
2/10
L6180 - L6181
ELECTRICAL CHARACTERISTICS
(V
CC
= 5V
±5%;
V
CM
= -7 to 7V; Tamb = 0 to 70°C;
V
SS
= -9 to 13.5V; V
DD
= 9 to 13.5V; unless otherwise specified.)
Symbol
V
IN
Parameter
Input Current
Test Condition
(See Fig.1 and note2)
V
CC
= 0 to 5.25V;
V
SS
, V
DD
= 0 to 13.5V
V
IN
= - 10 to 10V
V
IN
= - 15 to 15V
V
IA
or V
IB
= 3 to 15V; (see fig.1)
R
I
=
V
FS
V
OH
V
OL
V
IT2
I
IH2
I
IH1
V
H
V
IOC1
Failsafe Output Voltage
High Level Output Voltage
Low Level Output Voltage
V
IOH
Comparator Threshold
Voltage
High Operating Threshold
Voltage
Low Operating Threshold
Voltage
Input Hysteresis Voltage
Open Circuit Input Voltage
[(V
IA
or V
IN
) −V
IOC
]
I
IN
2.7
2.7
0.4
1.8
-25
-125
50
0.6
2.2
2.6
-75
-175
150
2
V
V
V
V
mV
mV
mV
V
3
Min.
Typ.
Max.
Unit
±3
±4.25
7
mA
mA
KΩ
R
I
Input Resistance
I
O
= -440µA (See Fig.3)
V
CC
= 4.75V; V
ID
= -1V;
I
OH
= -440µA
V
CC
= 5.25V; V
ID
= -1V;
I
OL
= 2mA
(See Fig.4)
V
OL
= 0.4V; I
OL
= 2mA;
(See Fig.4)
V
OH
= 2.7V; I
O
= -440µA
(See Fig.4)
|V
TH2
- V
TH1
|
Measured in accordance with
V.28 and RS-232D
(see note 4 and 7)
Measured in presence of AC
Input Signal (see note 7)
V
CC
= 5.25V; V
O
= 0; V
ID
= 1V;
(see note 5)
(see Figure 7 and note 11)
V
CC
= 4.75V to 5.25V; (see note 6)
V
dd
= 9 to 3.5V; (see note 6)
V
SS
= -9 to 13.5V; (see note 6)
V
CC
= 5.25V; V
O
= 0; V
ID
= 1V;
(see note 5)
R
L
= 390Ω; C
L
= 50pF;
|V
IN
= 1V|; (see fig 5 test Circuit
Fig. 6)
R
L
= 390Ω; C
L
= 50pF;
|V
IN
= 1V|; (see fig 5 test Circuit
Fig. 6)
(see note 7A)
(see note 7B)
R
L
= 390Ω; C
L
= 50pF;
|V
IN
| = 1V;(see fig. 5; Test
Circuit Fig. 6)
R
L
= 390Ω; C
L
= 50pF;
|V
IN
| = 1V;(see fig. 5; Test
Circuit Fig. 6)
V
IN
= 200mVpp; (see fig. 8 and
note 7;
V
IOCH
I
OS
V
IBV
C
I
V
CC
V
dd
V
SS
I
OS
T
plh
Open Circuit Input Voltage
Open Short Circuit Current
Input for Balance Test
Input Capacitance
Supply Current
Supply Current
Supplyt Current
Open Short Circuit Current
Propagation Delay Low to High
3.5
20
4
4.5
100
0.4
100
100
30
30
V
mA
V
pF
mA
mA
mA
mA
ns
20
0
100
1500
T
phl
Propagation Delay Low to High
0
1500
ns
V
IOCH
V
IOCL
V
ist
Delay V
IOCL
to V
IOCH
Switching
Delay V
IOCH
to V
IOCL
Switching
|T
plh
- T
phl
|
5
200
0
500
ms
ms
ns
T
SKEW1
Skew between rec’s in PKg Tp
(1) hl/1h - Tp (2) hl/1h
Frequency Accepted
(Receiver will Output)
0
300
ns
f
A
100
KHz
3/10
L6180 - L6181
ELECTRICAL CHARACTERISTICS
(V
CC
= 5V
±5%;
V
CM
= -7 to 7V; Tamb = 0 to 70°C;
V
SS
= -9 to 13.5V; V
DD
= 9 to 13.5V; unless otherwise specified.)
Symbol
f
R
Parameter
Frequency Rejected
(No Receiver Output)
Test Condition
V
IN
= 2Vpp;
(see fig. 8 and note 7)
Min.
Typ.
5
Max.
Unit
MHz
Note:
1) The algebric convention, where the less positive (more negative) is designed the minimum
2) With the voltage V
IA
or (V
IB
) ranging between
±15V,
while V
IB
or (V
IA
) is open or grounded, the resultant input current I
IA
or (I
IB
) shall remain
within the shaded region shown in the graph in Fig.1.
3) Either Point B’ or Point A’ is grounded in Figure 1
4) V
ICC
measured from grounded to (+) input with (-) input grounded
V
ICC
measured from grounded to (+) input with (-) input grounded
5) Not more than one output should be shorted at a time and for less than 1 seond
6) The sum of the product of the maximum supply currents and voltages cannot exceed themaximum power dissipation
7)
8)
A: The conditions for the inpit switching from V
IOCL
to V
IOCH
mode is: V
id
in start bit ”spacing condition”for less than TpV
ioch
(5ms).
B: The conditions for the input switching from V
IOCH
to V
IOCL
mode is: Vid > W
W2
for greater than TpV
IOCL
(200ms)
An example of a frequency response plot meeting the rejection/acceptance requirements is provided in figure 8.
LINE TRANSIENT IMMUNITY
(Considering the following cases; powered ON, Powered OFF-LOW im-
pedance power supply and powered OFF-HIGH impedance supply)
Symbol
ESD
EOS
Note:
9) All pins are required to withstand this parameters.
10) Input pins are required to withstand fig.2 without any degradation to the circuit.
11) The balance test requirement can be met by use of a current limit circuit which reduces the input bias current I
ib
(see figure 7)
for input voltages below a threshold voltage given by (I
ib
x 1K) - 400mV.
Parameter
Static
Stress
Test Condition
tested per MIL-STD-883
(see note 9)
transient pulse both polarities
for 100µs (see note 9 and Fig. 2)
Min.
2
50
Typ.
Max.
Unit
KV
V
Figure 1:
Input Current Voltage Mesurements
4/10
L6180 - L6181
Figure 2:
EOS Requiremets
Figure 3:
Output Failsafing
The output assumes a logic ”1”under the following conditions, (see figure 3)
1 Both inputs open
2 Both inputs shorted
3 Signal Opencircuit
3a Common grounded, signal open circuit
4 Common open, generator powered-on
5 Generatorpowered-down (see note 7)
6 Common open, generator powered-down
6a Signal grounded, common open, generator powered-down
7 Less than 250mVpp differential signal
5/10
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