74ALVCH16543
Rev. 3 — 15 December 2017
16-bit D-type registered transceiver; 3-state
Product data sheet
1
General description
The 74ALVCH16543 is a dual octal registered transceiver. Each section contains two
sets of D-type latches for temporary storage of the data flow in either direction.
Separate latch enable (nLEAB, nLEBA) and output enable (nOEAB, nOEBA) inputs are
provided for each register to permit independent control in either direction of the data
flow.
The 74ALVCH16543 contains two sections each consisting of two sets of eight D-type
latches with separate inputs and controls for each set. For data flow from A to B,
for example, the A-to-B enable (nEAB) inputs must be LOW in order to enter
data from nA0 to nA7, or take data from nB0 to nB7, as indicated in the function
table. With nEAB LOW, a LOW signal on the A-to-B latch enable (nLEAB) input
makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the
nLEAB signal stores the A data into the latches. With nEAB and nOEAB both LOW,
the 3-state B output buffers are active and display the data present at the output of
the A latches. Similarly, the nEBA, nLEBA and nOEBA signals control the data flow
from B-to-A.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic
level.
2
Features and benefits
•
•
•
•
•
•
•
•
•
•
CMOS low power consumption
Direct interface with TTL levels
MULTIBYTE flow-through standard pin-out architecture
Back-to-back registers for storage
Output drive capability 50 Ω transmission lines at 85 °C
All data inputs have bushold
Low inductance multiple V
CC
and GND pins for minimize noise and ground bounce
Current drive ±24 mA at V
CC
= 3.0 V.
3-state non-inverting outputs for bus oriented applications
Complies with JEDEC standards:
–
JESD8-5 (2.3 V to 2.7 V)
–
JESD8B/JESD36 (2.7 V to 3.6 V)
•
ESD protection:
–
HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
–
CDM JESD22-C101E exceeds 1000 V
Nexperia
16-bit D-type registered transceiver; 3-state
74ALVCH16543
5.2 Pin description
Table 2. Pin description
Symbol
1A0, 1A1, 1A2, 1A3, 1A4, 1A5, 1A6, 1A7
2A0, 2A1, 2A2, 2A3, 2A4, 2A5, 2A6, 2A7
1B0, 1B1, 1B2, 1B3, 1B4, 1B5, 1B6, 1B7
2B0, 2B1, 2B2, 2B3, 2B4, 2B5, 2B6, 2B7
1OEAB, 2OEAB
1OEBA, 2OEBA
1EAB, 2EAB
1EBA, 2EBA
1LEAB, 2LEAB
1LEBA, 2LEBA
GND
V
CC
Pin
5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24
52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33
1, 28
56, 29
3, 26
54, 31
2, 27
55, 30
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
Description
data inputs/outputs
data inputs/outputs
data inputs/outputs
data inputs/outputs
A to B output enable inputs (active LOW)
B to A output enable inputs (active LOW)
A to B enable inputs (active LOW)
B to A enable inputs (active LOW)
A to B latch enable inputs (active LOW)
B to A latch enable inputs (active LOW)
ground (0 V)
supply voltage
6
Functional description
[1]
Table 3. Function selection
Inputs
Outputs
nLEAB or nLEBA nAn or nBn
X
X
L
L
↑
↑
L
L
H
X
X
h
l
h
l
H
L
X
nBn or nAn
Z
Z
Z
Z
H
L
H
L
NC
X
H
↑
↑
L
L
L
L
L
Status
disabled
disabled
disabled + latch
disabled + latch
latch + display
latch + display
transparent
transparent
hold
nOEAB or nOEBA nEAB or nEBA
H
X
L
L
L
L
L
L
L
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH transition of nLEAB, nLEBA, nEAB or nEBA;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH transition of nLEAB, nLEBA, nEAB or nEBA;
X = don’t care;
↑ = LOW-to-HIGH transition of nLEAB, nLEBA, nEAB or nEBA;
NC = no change;
Z = high-impedance OFF-state.
74ALVCH16543
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 15 December 2017
5 / 17
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