DEMO MANUAL DC890B
DC890B QuickStart Guide
DESCRIPTION
Demonstration circuit DC890B along with PScope™ soft-
ware provides a USB based Windows PC hosted digital
data acquisition system supporting CMOS/LVDS output
ADCs up to 250Msps. The DC890B must be powered from
an external 6VDC ±0.5VDC power supply when operat-
ing in LVDS mode. When operating in CMOS mode, the
external power supply is optional. The Linear Technology
supplied PScope evaluation software automatically detects
the DC890B and can also detect many of the standard
ADC demonstration circuits boards.
The DC890B will
not enable LVDS mode unless an external 6.0VDC power
source is available.
This system provides for fast and easy
performance evaluation of high speed ADCs. DC890B
collects up to 256K word samples and then performs
various analyses on the data including calculating SNR,
SINAD, THD, SFDR and ENOB. The digitized input, an FFT
of the collected data, the primitive wave of the sample set
or an IFFT of modified frequency domain data is plotted to
a display window to facilitate analyzing distortion products
and sources. Figure 1 shows a picture of the DC890B. The
DC890B is connected to the ADC demonstration circuit via
a 100-pin edge connector, to the PC by a USB A-B cable and
to an optional power supply either by a 5mm power plug
or optionally by turrets. Figure 2 details the connections.
Design files for this circuit board are available at
http://www.linear.com/demo
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners.
BOARD PHOTO
Figure 1. DC890B Board
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DEMO MANUAL DC890B
OPERATING PRINCIPLES
The DC890B is capable of collecting a block of data samples
from an ADC demonstration circuit initiated either by an
internally generated trigger or an externally supplied 2.5V
CMOS level trigger of user selected edge. The external
trigger is TTL or CMOS compatible (the trigger line is
diode clamped to the 2.5V Rail through a 475Ω resistor).
Refer to the PScope software help for information on the
various operating modes and options. The conversion
clock to the DC890B is supplied via the ADC demonstra-
tion circuit either from an optional on board oscillator if
installed or an external signal generator connected to the
ADC demonstration circuit.
QUICK START PROCEDURE
To prevent damage to the DC890B, it is important to follow
the equipment setup procedure outlined below:
1. Do not plug the DC890B into the PC USB port before
running the installation program
2. Download the PScope installation program from
http://www.linear.com/software/.
3. Run the PScope installation program and follow the
on-screen instructions.
NOTE:
The PScope evaluation software requires a PC
running Windows98, 2000, XP or later, with an available
,
USB port.
4. Connect the DC890B to the USB port and supply ex-
ternal power to the DC890B, if you will be using the
LVDS mode. Do not use a USB cable longer than 2m or
the board may not reset properly. (See note in Trouble
Shooting section.)
5. Connect only 2.5V CMOS or LVDS output ADC demon-
stration circuits directly to the DC890B via the 100 pin
edge connector. All Linear Technology DC890 compat-
ible demo boards meet these requirements. Apply DC
power to the ADC demonstration circuit.
6. Each ADC demonstration board also comes with a quick
start guide similar to this one and should be referred to
for specific usage details relevant to the demonstration
circuit being evaluated. Please refer to it for proper
jumper settings, input power requirements and input
signal levels and frequency ranges.
7. Apply an appropriate conversion clock and analog input
signal to the ADC demonstration board.
8. ADC board will be automatically detected and config-
ured.
9. Select processing options (the hammer icon) menu
and verify that under trigger mode, no trigger wait is
selected
10. Enter the exact sample rate in MHz and select the sample
size in the provided fields in PScope page 1.
NOTE:
Minimum sample rate in LVDS mode is 50Msps.
11. If the sampled signal is not coherent with the encode
clock, select an appropriate windowing function from
the pull down menu.
12. Initiate a data collection cycle by clicking the green
collect button; it will turn red during the collection
cycle. An FFT should appear on the screen along with
a plot of the sampled data. Make sure the input level is
not over ranging the ADC. See online help for specific
guidance on using the PScope software.
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DEMO MANUAL DC890B
QUICK START PROCEDURE
EXT TRIGGER INPUT
JTAG
EXT 6VDC
REQUIRED FOR
LVDS. APPLY TO
TURRET TP2 AND
TP3 OR USE A 5mm
POWER-PLUG
0R WALL
TRANSFORMER
DEMONSTRATION
CIRCUIT
CONNECTOR
USB
CONNECTOR
Figure 2. DC890B Basic Connection Locations
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DEMO MANUAL DC890B
USEFUL SOFTWARE TOOLS
The PScope software includes tools for automatic software
updates and for quickly retrieving documentation from
the world wide web.
NOTE:
Adobe Acrobat Reader is required to view the docu-
ments and is available at
http://www.adobe.com.
To update the PScope software (requires an internet
connection):
• Choose Update Program from the tools menu.
This automatically updates the main program and drivers
for individual demo circuits.
OPTIONAL CONNECTIONS TO THE DC890B
• In CMOS mode the DC890B can operate from the USB
power, however in LVDS mode, the Spartan-III FPGA IO
ring drivers draw considerable supply current to bias
the active LVDS terminations. The DC890B has provi-
sions for a 5mm power plug for an external 6V ±0.5V
supply. The DC890B automatically detects the presence
of external power and disables the USB power input.
• X1: The DC890B has provisions for an external trigger
input, edge selectable by software. This permits initiat-
ing data block capture by an external event.
• J2: A JTAG connector is provided for downloading
custom FPGA software to the board. Grounding pin 3
of J2 automatically puts the FPGA into JTAG program-
ming mode. User developed code can be loaded into the
FPGA without compromising the factory installed code.
Jumper pins 4 and 6 of PIC programming connector
J1 to disable the microcontroller when using custom
FPGA code. Refer to the schematic for further details.
This feature is provided due to customer requests.
Development of custom code will not be supported
by the factory.
• J7 and J8 locations (not installed) provide access to
six additional FPGA pins for test purposes. These pins
also drive LED indicators useful for debug purposes.
Xilinx provides logic analysis and data collection features
through JTAG via ChipScope.
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DEMO MANUAL DC890B
LED INDICATORS
The DC890B provides system status via eight LEDs:
LED-1. TRANSFER – Indicates a USB data transfer from
the PScope to the PC is in progress.
LED-2. SEEP – Indicates access of the optional demon-
stration circuit serial electrically erasable PROM on
select demonstration boards. Information in this
SEEP permits PScope software to configure the
DC890B properly for the device under evaluation
using the auto detect demo board feature in the
configure/device menu.
LED-3. RST – Indicates assertion of either a hard or soft
reset.
LED-4. DCM_RDY– In LVDS mode, LED 4 blinks to alert
the user that the sample clock is either not present
or outside the required frequency range (F
IN
must
be > 50 MHz). A steady on condition indicates the
digital clock module is locked to the input sample
clock. In CMOS mode LED 4 functions as a power-
on/FPGA programmed Indicator.
LED-5. RUN ON TRIGGER – Indicates that the board is
set to run on trigger (versus halt on trigger mode).
LED-6. DATA_RDY – Indicates completion of data block
acquisition.
LED-7. RUN – Indicates the board is ARMED to collect a
block of data.
LED-8. TRIGGER – Indicates that a trigger was received
and data collection has started.
CIRCUIT DETAILS
A schematic, parts list and parts placement drawings are
attached to the end of this quick start guide for reference
only.
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