Door Module Power IC
TLE 8201R
Data Sheet Rev. 2.0
Features
• Full bridge (150mΩ) for main doorlock motor
• Two half-bridges (400mΩ) for deadbolt and mirror
position motor or mirror fold motor
• Two half-bridges (800mΩ) for mirror position
• High-side switch (100mΩ) for mirror defrost
• Four high-side switches (500mΩ) for 5W and 10W
lamps
• Current sense analog output with multiplex
• All outputs with short circuit protection and diagnosis
• Over-temperature protection with warning
• Open load diagnosis for all outputs
• Charge pump-Output for n-channel MOS-FET reverse-polarity protection
• Very low current consumption in sleep mode
• Standard 16-bit SPI for control and diagnosis
• Over-and Undervoltage Lockout
• Power-SO package with full-size heatslug for excellent low thermal resistance
Type
TLE 8201R
Functional Description
The TLE 8201R is an Application Specific Standard Product for automotive door-module
applications. It includes all the power stages necessary to drive the loads in a typical front
door application, i.e. central lock, deadlock or mirror fold, mirror position, mirror defrost
and 5W or 10W lamps, e.g for turn signal, courtesy/warning or control panel illumination.
It is designed as a monolithic circuit in Infineons mixed technology SPT which combines
bipolar and CMOS control circuitry with DMOS power devices.
Short circuit and over-temperature protection and a detailed diagnosis are in line with the
safety requirements of automotive applications. The current sense output allows to
improve the total system performance. The standard SPI interface saves microcontroller
I/O lines while still giving flexible control of the power stages and a detailed diagnosis.
Ordering Code
-
Package/Shipment
PG-DSO-36-27
Data Sheet Rev. 2.0
1
2006-06-07
TLE 8201R
Table of Contents
1
2
2.1
2.2
3
3.1
3.2
3.3
4
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.2
4.2.1
4.2.2
4.2.3
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.4
4.4.1
4.4.2
4.5
4.5.1
4.5.2
4.6
4.6.1
4.6.2
4.7
4.7.1
5
6
Page
Block Diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
7
8
8
Block Description and Electrical Characteristics
. . . . . . . . . . . . . . . . . . 9
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Sleep-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reverse Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Monitoring Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power Supply Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Current Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Register Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SPI bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Status Register Address selection and Reset . . . . . . . . . . . . . . . . . . . . 20
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power-Outputs 1-6 (Bridge Outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Protection and Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Power-Output 7 (Mirror heater driver) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Protection and Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Power-Outputs 8 - 11 (Lamp drivers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Protection and Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Logic In- and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Application Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Package Outlines
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Data Sheet Rev. 2.0
2
2006-06-07
TLE 8201R
Block Diagram
1
Block Diagram
Vs
GO CP
Charge-
pump
RevPol
MOS driver
Fault-
Detect
Vcc
INH
CSN
CLK
DI
DO
PWM1
PWM2
ISO
Biasing
OUT1
OUT2
SPI
OUT3
Logic and Latch
Logic IN
current
sense MUX
OUT4
OUT5
OUT8
OUT9
OUT10
OUT11
GND
OUT7
OUT6
Figure 1
Block Diagram
Data Sheet Rev. 2.0
3
2006-06-07
TLE 8201R
Pin Configuration
2
2.1
Pin Configuration
Pin Assignment
cooling tab
(GND)
GND
OUT5
OUT6
Vs
INH
PWM1
PWM2
ISO
Vcc
DO
CLK
CSN
DI
GO
Vs
OUT1
OUT1
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
GND
n.c.
OUT4
Vs
OUT7
OUT7
Vs
OUT8
OUT9
CP
Vs
OUT10
OUT11
Vs
OUT3
OUT2
OUT2
GND
Figure 2
Pin Configuration PG-DSO-36-27
Data Sheet Rev. 2.0
4
2006-06-07
TLE 8201R
Pin Configuration
2.2
Pin
cooling
tab
1, 18,
19, 36
2
3
Pin Definitions and Functions
Symbol
GND
GND
OUT5
OUT6
Function
Cooling tab,
internally connected to GND; to reduce thermal
resistance place cooling areas and thermal vias on PCB.
Ground;
internally connected to cooling tab (heat slug).
Power-Output of half-bridge 5;
DMOS half-bridge
Power-Output of half-bridge 6;
DMOS half-bridge.
Power supply;
needs decoupling capacitors to GND. > 47µF
electrolytic in parallel with 100nF ceramic is recommended. All
Vs pins must be connected externally
Inhibit;
active low. Sets the device in sleep mode with low
current consumption when left open or pulled to LOW. Has an
internal pull down current source
Logic Input for direct power stage control;
direct input to
control the high-side switches selected by the SPI xsel1 bits in
control register CtrlReg01
Logic Input for direct power stage control;
direct input to
control the switches selected by the SPI xsel2 bits in control
register CtrlReg11
Current sense output;
Mirrors the current of the high-side
switch selected by the current sense multiplexer control bits ISx
Logic Supply Voltage;
needs decoupling capacitors to GND
(pin 1). 10µF electrolytic in parallel with 10nF ceramic is
recommended
Serial Data Output;
Transfers data to the master when the chip
is selected by CSN=LOW. Data transmission is synchronized by
CLK, DO state is changed on the rising edge of CLK. The most
significant bit (MSB) is transferred first. The pin is tristated as
long as CSN=HIGH
Serial Data Clock Input;
Receives the clock signal from the
master and clocks the SPI shift register. Has an internal pull
down current source
Serial Port Chip Select Not Input;
SPI communication is
enabled by pulling CSN to LOW. CLK must be LOW during the
transition of CSN. The CSN-pin has an internal pull-up current
source
5
2006-06-07
4, 15, 23, Vs
26, 30, 33
5
INH
6
PWM1
7
PWM2
8
9
ISO
Vcc
10
DO
11
CLK
12
CSN
Data Sheet Rev. 2.0
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