DS87C550
EPROM High-Speed Microcontroller
with ADC and PWM
www.maxim-ic.com
FEATURES
§
87C52 Compatible
- 8051 pin and instruction set compatible
- Three 16-bit timer/counters
- 256 bytes scratchpad RAM
On-Chip Memory
- 8kB EPROM (OTP & Windowed Packages)
- 1kB extra on-chip SRAM for MOVX access
On-Chip Analog-to-Digital Converter
- Eight channels of analog input, 10-bit
resolution
- Fast conversion time
Pulse-Width Modulator Outputs
- Four channels of 8-bit PWM
- Channels cascadable to 16-bit PWM
Four Capture plus Three Compare Registers
55 I/O Port Pins
New Dual Data Pointer Operation
- Either data pointer can be incremented or
decremented
ROMSIZE Feature
- Sets effective on-chip ROM size from 0 - 8kB
- Allows access to entire external memory map
- Dynamically adjustable by software
High-Speed Architecture
- 4 clocks/machine cycle (8051 = 12)
- Runs DC to 33MHz clock rates
- Single-cycle instruction in 121ns
- New Stretch Cycle feature allows access to
fast/slow memory or peripherals
Unique Power Savings Modes
EMI Reduction Mode Disables ALE if Not
Needed
High-Integration Controller Includes:
- Power-fail reset
- Early-warning power-fail interrupt
- Two full-duplex hardware serial ports
- Programmable watchdog timer
16 Total Interrupt Sources with Six External
Available in 68-Pin PLCC, 80-Pin PQFP, and
68-Pin Windowed CLCC
PIN CONFIGURATIONS
TOP VIEW
9
1
61
§
§
10
60
DS87C550
§
§
§
§
§
26
44
27
43
PLCC, Windowed CLCC
80
65
§
1
64
DS87C550
§
§
§
§
§
24
41
The High-Speed Microcontroller User’s Guide and High-Speed
Microcontroller User’s Guide: DS87C550 Supplement must be used
in conjunction with this data sheet.
Download them at
www.maxim-ic.com/user_guides.
25
40
PQFP
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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REV: 070505
DS87C550 EPROM High-Speed Microcontroller with ADC and PWM
DESCRIPTION
The DS87C550 EPROM High-Speed Microcontroller with ADC and PWM is a member of the fastest
100% 8051-compatible microcontroller family available. It features a redesigned processor core that
removes wasted clock and memory cycles. As a result, it executes 8051 instructions up to three times
faster than the original architecture for the same crystal speed. The DS87C550 also offers a maximum
crystal speed of 33MHz, resulting in apparent execution speeds of up to 99MHz.
The DS87C550 uses an industry standard 8051 pin-out and includes standard resources such as three
timer/counters, and 256 bytes of scratchpad RAM. This device also features 8kB of EPROM with an
extra 1kB of data RAM (in addition to the 256 bytes of scratchpad RAM), and 55 I/O ports pins. Both
One-Time-Programmable (OTP) and windowed packages are available.
Besides greater speed, the DS87C550 includes a second full hardware serial port, seven additional
interrupts, a programmable watchdog timer, brownout monitor, and power-fail reset.
The DS87C550 also provides dual data pointers (DPTRs) to speed block data memory moves. The user
can also dynamically adjust the speed of external accesses between two and 12 machine cycles for
flexibility in selecting memory and peripherals.
Power Management Mode (PMM) is useful for portable or battery-powered applications. This feature
allows software to select a lower speed clock as the main time base. While normal operation has a
machine cycle rate of 4 clocks per cycle, the PMM allows the processor to run at 1024 clocks per cycle.
For example, at 12MHz, standard operation has a machine cycle rate of 3MHz. In Power Management
Mode, software can select an 11.7 kHz (12MHz/1024) machine cycle rate. There is a corresponding
reduction in power consumption due to the processor running slower.
The DS87C550 also offers two features that can significantly reduce electromagnetic interference (EMI).
One EMI reduction feature allows software to select a reduced emission mode that disables the ALE
signal when it is unneeded. The other EMI reduction feature controls the current to the address and data
pins interfacing to external devices producing a controlled transition of these signals.
Designers using the DS87C550 as an upgrade for the 87C552 or similar 8051-based microcontrollers
with A/D capability should read
Application Note 2: The DS87C550 as an Upgrade for 8051 Derivatives.
ORDERING INFORMATION
PART
DS87C550-QCL
DS87C550-QCL+
DS87C550-FCL
DS87C550-FCL+
DS87C550-QNL
DS87C550-QNL+
DS87C550-FNL
DS87C550-FNL+
DS87C550-KCL*
MAX CLOCK
SPEED (MHz)
33
33
33
33
33
33
33
33
33
TEMP RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
PIN-PACKAGE
68 PLCC
68 PLCC
80 PQFP
80 PQFP
68 PLCC
68 PLCC
80 PQFP
80 PQFP
68 Windowed CLCC
+
Denotes a Pb-free/RoHS-compliant device.
*
The windowed ceramic LCC package is intrinsically Pb free.
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DS87C550 EPROM High-Speed Microcontroller with ADC and PWM
DS87C550 BLOCK DIAGRAM
Figure 1
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DS87C550 EPROM High-Speed Microcontroller with ADC and PWM
PIN DESCRIPTION
Table 1
PLCC/
CLCC
2
36
37
15
QFP
72
34
35
9
SIGNAL NAME
V
CC
GND
RST
V
CC
-
Digital +5V power input.
GND –
Digital ground.
RST - I/O.
The RST input pin contains a Schmitt voltage input to recognize
external active high Reset inputs. The pin also employs an internal pulldown
resistor to allow for a combination of wired OR external Reset sources. An RC is
not required for power-up, as the DS87C550 provides this function internally. This
pin also acts as an output when the source of the reset is internal to the device (i.e.,
watchdog timer, power-fail, or crystal-fail detect). In this case, the RST pin will be
held high while the processor is in a Reset state, and will return to low as the
processor exits this state. When this output capability is used, the RST pin should
not be connected to an RC network or a logic output driver.
Input -
The crystal oscillator pins XTAL1 and XTAL2 provide support for
fundamental mode, parallel resonant, AT cut crystals. XTAL1 acts also as an input
if there is an external clock source in place of a crystal. XTAL2 serves as the
output of the crystal amplifier. Note that this output cannot be used to drive any
additional load when a crystal is attached as this can disturb the oscillator circuit.
- Output.
The Program Store Enable output. This signal is commonly
connected to optional external ROM memory as a chip enable.
PSEN
will provide
an active low pulse during a program byte access, and is driven high when not
accessing external program memory.
ALE - Output.
The Address Latch Enable output functions as a clock to latch the
external address LSB from the multiplexed address/data bus on Port 0. This signal
is commonly connected to the latch enable of an external 373 family transparent
latch. ALE is driven high when the DS87C550 is in a Reset condition. ALE can
also be disabled and forced high using the EMI reduction mode ALEOFF.
EA
- Input.
An active low input pin that when connected to ground will force the
DS87C550 to use an external program memory. The internal RAM is still
accessible as determined by register settings.
EA
should be connected to V
CC
to
use internal program memory. The input level on this pin is latched at reset.
Port 1 - I/O.
Port 1 functions as both an 8-bit, bi-directional I/O port and an
alternate functional interface for several internal resources. The reset condition of
Port 1 is all bits at logic 1. In this state, a weak pullup holds the port high. This
condition allows the pins to serve as both input and output. Input is possible since
any external circuit whose output drives the port will overcome the weak pullup.
When software writes a 0 to any Port 1 pin, the DS87C550 will activate a strong
pulldown that remains on until either a 1 is written or a reset occurs. Writing a 1
after the port has been at 0 will cause a strong transition driver to turn on, followed
by a weaker sustaining pullup. Once the momentary strong driver turns off, the
port again returns to a weakly held high output (and input) state. The alternate
functions of Port 1 pins are detailed below. Note that when the Capture/Compare
functions of timer 2 are used, the interrupt input pins become capture trigger
inputs.
PSEN
DESCRIPTION
35
34
32
31
XTAL1
XTAL2
47
48
PSEN
48
49
ALE
49
50
EA
16-23
10-17
P1.0-P1.7
16
17
18
19
20
21
22
23
10
11
12
13
14
15
16
17
Port
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Alternate Function
INT2/CT0 External Interrupt 2/Capture Trigger 0
INT3/CT1 External Interrupt 3/Capture Trigger 1
INT4/CT2 External Interrupt 4/Capture Trigger 2
INT5/CT3 External Interrupt 5/Capture Trigger 3
T2
External I/O for Timer/Counter 2
T2EX
Timer/Counter 2 Capture/Reload Trigger
RXD1
Serial Port 1 Input
TXD1
Serial Port 1 Output
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DS87C550 EPROM High-Speed Microcontroller with ADC and PWM
PLCC/
CLCC
50-57
57
56
55
54
53
52
51
50
39-46
39
40
41
42
43
44
45
46
24-31
QFP
51-58
58
57
56
55
54
53
52
51
38-42
45-47
38
39
40
41
42
45
46
47
18-20
23-27
SIGNAL NAME
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
P2.0 (A8)
P2.1 (A9)
P2.2 (A10)
P2.3 (A11)
P2.4 (A12)
P2.5 (A13)
P2.6 (A14)
P2.7 (A15)
P3.0-P3.7
DESCRIPTION
Port 0-I/O - AD0-7.
Port 0 is an open-drain 8-bit, bi-directional general-purpose
I/O port. When used in this mode pullup resistors are required to provide a logic 1
output. As an alternate function, Port 0 operates as a multiplexed address/data bus
to access off-chip memory or peripherals. In this mode, the LSB of the memory
address is output on the bus during the time that ALE is high. When ALE falls to
a logic 0, the port transitions to a bi-directional data bus. In this mode, the port
provides active high drivers for logic 1 output. The reset condition of Port 0 is tri-
state (i.e., the open drain devices are off).
Port 2-I/O Address A15:A8.
Port 2 functions as an 8-bit bi-directional I/O port
or alternately as an external address bus (A15-A8). The reset condition of Port 2 is
logic high I/O state. In this state, weak pullups hold the port high allowing the
pins to be used as an input or output as described above for Port 1. As an alternate
function Port 2 can function as MSB of the external address bus. This bus can be
used to read external memory or peripherals.
Port 3 - I/O.
Port 3 functions as an 8-bit bi-directional I/O port or alternately as
an interface for External Interrupts, Serial Port 0, Timer 0 & 1 Inputs, and
RD
and
WR
strobes. When functioning as an I/O port, these pins operate as indicated
above for Port 1. The alternate modes of Port 3 are detailed below.
Port Alternate Mode
P3.0 RXD0
Serial Port 0 Input
P3.1 TXD0
Serial Port 0 Output
INT0
External Interrupt 0
P3.2
INT1
External Interrupt 1
P3.3
P3.4 T0
Timer 0 External Input
P3.5 T1
Timer 1 External Input
WR
External Data Memory Write Strobe
P3.6
RD
External Data Memory Read Strobe
P3.7
Port 4 - I/O.
Port 4 functions as an 8-bit bi-directional I/O port or alternately as
an interface to Timer 2’s Capture Compare functions. When functioning as an I/O
port, these pins operate as indicated in the Port 1 description. The alternate modes
of Port 4 are detailed below.
Port 4
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
Alternate Mode
CMSR0
Timer 2 compare match set/reset output 0
CMSR1
Timer 2 compare match set/reset output 1
CMSR2
Timer 2 compare match set/reset output 2
CMSR3
Timer 2 compare match set/reset output 3
CMSR4
Timer 2 compare match set/reset output 4
CMSR5
Timer 2 compare match set/reset output 5
CMT0
Timer 2 compare match toggle output 0
CMT1
Timer 2 compare match toggle output 1
24
25
26
27
28
29
30
31
7-14
18
19
20
23
24
25
26
27
80
1-2
4-8
P4.0-P4.7
7
8
9
10
11
12
13
14
80
1
2
4
5
6
7
8
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