19-4859; Rev 8/09
DS80C310
High-Speed Microcontroller
www.maxim-ic.com
GENERAL DESCRIPTION
The DS80C310 is a fast 80C31/80C32-compatible
microcontroller. It features a redesigned processor
core without wasted clock and memory cycles. As a
result, it executes every 8051 instruction between 1.5x
and 3x faster than the original architecture for the
same crystal speed. Typical applications have a speed
improvement of 2.5x using the same code and the
same crystal. The DS80C310 offers a 25MHz
maximum crystal speed, resulting in apparent
execution speeds of 62.5MHz (approximately 2.5x).
The DS80C310 is pin compatible with the standard
80C32 and includes standard resources such as three
timer/counters, 256 bytes of RAM, and a serial port. It
also provides dual data pointers (DPTRs) to speed
block data memory moves. It also can adjust the speed
of MOVX data memory access between two and nine
machine cycles for flexibility in selecting external
memory and peripherals. The DS80C310 offers
upward compatibility with the DS80C320.
PIN CONFIGURATIONS
TOP VIEW
FEATURES
80C32 Compatible
8051 Pin and Instruction Set Compatible
Full-Duplex Serial Port
Three 16-Bit Timer/Counters
256 Bytes Scratchpad RAM
Multiplexed Address/Data Bus
Addresses 64kB ROM and 64kB RAM
High-Speed Architecture
4 Clocks/Machine Cycle (8051 = 12)
Runs DC to 25MHz Clock Rates
Single-Cycle Instruction in 160ns
Dual Data Pointer
Optional Variable Length MOVX to Access
Fast/Slow RAM /Peripherals
10 Total Interrupt Sources with 6 External
Internal Power-On Reset Circuit
Upwardly Compatible with the DS80C320
Available in 40-Pin Plastic DIP, 44-Pin PLCC,
and 44-Pin TQFP
Note:
Designers must have two documents to fully use all the features
of this device: this data sheet and the High-Speed Microcontroller
User’s Guide, available on our website at
www.maxim-
ic.com/microcontrollers
. Data sheets contain pin descriptions,
feature overviews, and electrical specifications, whereas the user’s
guide contains detailed information about device features and
operation.
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
1 of 22
DS80C310
ORDERING INFORMATION
PART
DS80C310-MCG
DS80C310-MCG+
DS80C310-QCG
DS80C310-QCG+
DS80C310-QNG
DS80C310-QNG+
DS80C310-ECG
DS80C310-ECG+
TEMP RANGE
0C to +70C
0C to +70C
0C to +70C
0C to +70C
-40C to +85C
-40C to +85C
0C to +70C
0C to +70C
MAX CLOCK
SPEED (MHz)
25
25
25
25
25
25
25
25
PIN-PACKAGE
40 Plastic DIP
40 Plastic DIP
44 PLCC
44 PLCC
44 PLCC
44 PLCC
44 TQFP
44 TQFP
+
Denotes a lead(Pb)-free/RoHS-compliant device.
Figure 1. Block Diagram
DS80C310
2 of 22
DS80C310
PIN DESCRIPTION
PDIP
PIN
PLCC
TQFP
NAME
FUNCTION
Port 1 (I/O). Port 1 functions as both an 8-bit bidirectional I/O port
and an alternate functional interface for Timer 2 I/O and new
external interrupts. The reset condition of Port 1 is with all bits at
logic 1. In this state, a weak pullup holds the port high. This
condition also serves as an input mode, since any external circuit
that writes to the port overcomes the weak pullup. When software
writes a 0 to any port pin, the DS80C310 activates a strong pulldown
that remains on until either a 1 is written or a reset occurs. Writing a
1 after the port has been at 0 causes a strong transition driver to turn
on, followed by a weaker sustaining pullup. Once the momentary
strong driver turns off, the port once again becomes the output high
(and input) state. The alternate modes of Port 1 are outlined as
follows:
PIN
PORT ALTERNATE
FUNCTION
PDIP PLCC TQFP
1–8
2–9
40–44,
1, 2, 3
P1.0–P1.7
External I/O for
Timer/Counter 2
Timer/Counter 2
Capture/Reload
2
3
41
P1.1
T2EX
Trigger
DS80C320 has a serial
3
4
42
P1.2
—
port RXD
DS80C320 has a serial
4
5
43
P1.3
—
port TXD
External Interrupt 2
5
6
44
P1.4
INT2
(Positive Edge Detect)
External Interrupt 3
6
7
1
P1.5
(Negative Edge
INT3
Detect)
External Interrupt 4
7
8
2
P1.6
INT4
(Positive Edge Detect)
External Interrupt 5
8
9
3
P1.7
(Negative Edge
INT5
Detect)
Reset (Input). The RST input pin contains a Schmitt voltage input to
recognize external active-high reset inputs. The pin also employs an
internal pulldown resistor to allow for a combination of wired-OR
external reset sources.
1
2
40
P1.0
T2
9
10
4
RST
3 of 22
DS80C310
PDIP
PIN
PLCC
TQFP
NAME
FUNCTION
Port 3 (I/O). Port 3 functions as both an 8-bit bidirectional I/O port
and an alternate functional interface for external Interrupts, Serial
Port 0, Timer 0 and 1 Inputs,
RD
and
WR
strobes. The reset
condition of Port 3 is with all bits at logic 1. In this state, a weak
pullup holds the port high. This condition also serves as an input
mode, since any external circuit that writes to the port will overcome
the weak pullup. When software writes a 0 to any port pin, the
DS80C310 will activate a strong pulldown that remains on until
either a 1 is written or a reset occurs. Writing a 1 after the port has
been at 0 will cause a strong transition driver to turn on, followed by
a weaker sustaining pullup. Once the momentary strong driver turns
off, the port once again becomes both the output high and input
state. The alternate modes of Port 3 are as follows:
PDIP
PIN
PLCC
11
TQFP
5
PORT
P3.0
ALTERNATE
RXD0
FUNCTION
10–17
11,
13–19
5, 7–13
P3.0–P3.7
18, 19
20, 21
1, 22,
23
24
25
26
27
28
29
30
31
14, 15
16, 17,
39
18
19
20
21
22
23
24
25
XTAL2,
XTAL1
GND
A8 (P2.0)
A9 (P2.1)
A10 (P2.2)
A11 (P2.3)
A12 (P2.4)
A13 (P2.5)
A14 (P2.6)
A15 (P2.7)
Serial Port 0
Input
Serial Port 0
11
13
7
P3.1
TXD0
Output
External Interrupt
INT0
12
14
8
P3.2
0
External Interrupt
INT1
13
15
9
P3.3
1
Timer 0 External
14
16
10
P3.4
T0
Input
Timer 1 External
15
17
11
P3.5
T1
Input
External Data
WR
Memory Write
16
18
12
P3.6
Strobe
External Data
RD
17
19
13
P3.7
Memory Read
Strobe
Crystal Oscillator Pins. XTAL1 and XTAL2 provide support for
parallel resonant, AT-cut crystals. XTAL1 also acts as an input in
the event that an external clock source is used in place of a crystal.
XTAL2 serves as the output of the crystal amplifier.
10
20
21
22
23
24
25
26
27
28
Digital Circuit Ground
Address Outputs (Port 2) (Output). Port 2 serves as the MSB for
external addressing. P2.7 is A15 and P2.0 is A8. The DS80C310
automatically places the MSB of an address on P2 for external ROM
and RAM access. Although Port 2 can be accessed like an ordinary
I/O port, the value stored on the Port 2 latch is never seen on the pins
(due to memory access). Therefore, writing to Port 2 in software is
only useful for the instructions MOVX A, @ Ri or MOVX @ Ri, A.
These instructions use the Port 2 internal latch to supply the external
address MSB; the Port 2 latch value is supplied as the address
information.
4 of 22
DS80C310
PDIP
29
PIN
PLCC
32
TQFP
26
NAME
PSEN
FUNCTION
Active-Low Program Store Enable (Output). This signal is
commonly connected to external ROM memory as a chip enable.
PSEN
is driven high when data memory (RAM) is being accessed
through the bus and during a reset condition.
Address Latch Enable (Output). The output functions as clock to
latch the external address LSB from the multiplexed address/data
bus on Port 0. This signal is commonly connected to the latch enable
of an external 373 family transparent latch. ALE is forced high when
the DS80C310 is in a reset condition.
Active-Low External Access (Input). This pin must be connected to
ground for proper operation.
Address/Data Bus 0–7 (Port 0) (I/O). Port 0 is the multiplexed
address/data bus. During the time when ALE is high, the LSB of a
memory address is presented. When ALE falls to logic 0, the port
transitions to a bidirectional data bus. This bus is used to read
external ROM and read/write external RAM memory or peripherals.
Port 0 has no true port latch and cannot be written directly by
software. The reset condition of Port 0 is high.
+5V Power Supply
No Connection (Reserved). These pins should not be connected.
They are reserved for use with future devices in this family.
30
33
27
ALE
31
32
33
34
35
36
37
38
39
40
–
35
36
37
38
39
40
41
42
43
44
12, 34
29
30
31
32
33
34
35
36
37
38
6, 28
EA
AD7 (P0.7)
AD6 (P0.6)
AD5 (P0.5)
AD4 (P0.4)
AD3 (P0.3)
AD2 (P0.2)
AD1 (P0.1)
AD0 (P0.0)
V
CC
N.C.
COMPATIBILITY
The DS80C310 is a fully static, CMOS, 8051-compatible microcontroller designed for high performance.
In most cases the DS80C310 can drop into an existing socket for the 80C31 or 80C32 to significantly
improve the operation. In general, software written for existing 8051-based systems works without
modification on the DS80C310. The exception is critical timing because the high-speed microcontroller
performs its instructions much faster than the original for any given crystal selection. The DS80C310 runs
the standard 8051 family instruction set and is pin compatible with DIP, PLCC, or TQFP packages. The
DS80C310 is a streamlined version of the DS80C320. It maintains upward compatibility but has fewer
peripherals.
The DS80C310 provides three 16-bit timer/counters, a full-duplex serial port, and 256 bytes of direct
RAM. I/O ports have the same operation as a standard 8051 product. Timers default to a 12 clock-per-
cycle operation to keep their timing compatible with original 8051 family systems. However, timers are
individually programmable to run at the new 4 clocks per cycle if desired.
The DS80C310 provides several new hardware functions that are controlled by Special Function
Registers (SFRs). Table 1 summarizes the SFRs.
PERFORMANCE OVERVIEW
The DS80C310 features a high-speed 8051-compatible core. Higher speed comes not just from increasing
the clock frequency but from a newer, more efficient design.
This updated core does not have the dummy memory cycles that exist in a standard 8051. A conventional
8051 generates machine cycles using the clock frequency divided by 12. In the DS80C310, the same
5 of 22
京公网安备 11010802033920号
EEWORLD
