DS1844E-100/T&R; datasheet, PDF

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DS1844E-100/T&R;: DescriptionIC POT DIG QUAD 100K 20-TSSOP; Categorysemiconductor Analog mixed-signal IC; File Size257KB，14 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html

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DS1844E-100/T&R; Overview

IC POT DIG QUAD 100K 20-TSSOP

DS1844E-100/T&R; Parametric

Parameter Name	Attribute value
cone	Linear
Configuration	Potentiometer
Number of circuits	4
Number of taps	64
Resistance (ohms)	100k
interface	I²C, serial
memory type	Volatile
Voltage - Power	2.7 V ~ 5.5 V
characteristic	Optional address
Tolerance	±20%
Temperature coefficient (typ.)	750 ppm/°C
Resistance - Vernier (Ohms) (Typical)	250
Operating temperature	-40°C ~ 85°C
Package/casing	20-TSSOP (0.173", 4.40mm wide)
Supplier device packaging	20-TSSOP

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DS1844

Quad Digital Potentiometer

www.maxim-ic.com

FEATURES

Four independent, digitally controlled 64-

position potentiometers

Two interface control options

- 5-wire serial

- 2-wire addressable

Standard resistance values

- DS1844-010 10 kW

- DS1844-050 50 kW

- DS1844-100 100 kW

Mixed resistor value combinations (contact

factory for availability)

Operating Temperature Range

- Industrial: -40°C to +85°C

PIN ASSIGNMENT

R/W, A0

A2, RST

GND

SCL, CLK

SDA, D

A1, D

OUT

20-Pin DIP (300-mil)

Device Description

20-Pin SOIC (300-mil)

20-Pin TSSOP (173-mil)

PIN DESCRIPTION

A0, A1, A2

SDA

SCL

RST

CLK

OUT

-H

-L

-W

GND

2.7V to 5.5V

Port Select

Device Select Pins (2-Wire)

Serial Data I/O (2-Wire)

Serial Clock (2-Wire)

Read/Write enable (5-Wire)

Serial Port Reset Input (5-Wire)

Serial Port Data Input (5-Wire)

Serial Port Clock Input (5-Wire)

Cascade Data Output (5-Wire)

High-end Terminal of Pot

Low-end Terminal of Pot

Wiper Terminal of Pot

Ground

DESCRIPTION

The DS1844 Quad Digital Potentiometer is a four-channel, digitally controlled linear potentiometer. Each

potentiometer is comprised of 63 equi-resistive sections and has three terminals accessible to the user.

These include the high side terminals, H

, the wiper terminals, W

, and the low-side terminals, L

The

wiper position on the resistor ladder is selected via an 8-bit register value. Communication and control of

the device are supported by two types of serial interface. These include a 5-wire I/O shift register

interface and a 2-wire addressable interface.

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053105

DS1844

The DS1844 is available in standard 10 kW, 50 kW, and 100 kW versions. Mixed resistor combinations

are also available through custom setups. The DS1844 is specified to operate over the industrial

temperature range: -40°C to +85°C. Packages for the DS1844 include 20-pin DIPs, SOICs, and TSSOPs.

OPERATION

The DS1844 contains four 64-position potentiometers. Each potentiometer is independent and has three

accessible terminals, which include H

, L

, and W

. Each potentiometer is comprised of 63 individual

resistor elements. Between each resistor element is a tap-point that is multiplexed to the wiper terminal,

. Additionally, the wiper terminal can be multiplexed directly to the end-terminals, H

and L

The DS1844 supports two interface control options. Both options allow for the direct placement of the

wiper position on the resistor ladder. Each wiper has an associated 6-bit register used to hold its positional

value.

The DS1844 is a volatile device and will always power-up with the wiper positions set to mid-tap

(position 32-decimal). The end-terminal H

will have wiper position value 63-decimal and the L

terminal

will have wiper position value 0-decimal. Because the DS1844 is a 64-position device only 6 bits of data

are necessary to write a wiper’s value. However, communication with the DS1844 will require using a

full 8 bits, with the remaining 2 bits specifying the potentiometer selected. A discussion of proper

communication protocol is provided under the section entitled Serial Port Operation. A block diagram of

the DS1844 is shown in Figure 1.

SERIAL PORT OPERATION

As stated, the DS1844 can support two types of serial interface control. This includes a 5-wire serial

interface and a 2-wire addressable interface. The type interface supported during operation is selectable

via the port select input pin, PS. Additionally, certain pins provide dual functionality dependent on the

serial port selected. The pin description table lists pin functionality according to the interface selected.

5-Wire Serial Port Control

The 5-wire serial interface provides an 8-bit I/O shift register for loading and reading wiper data. The 5-

wire serial interface control is selected when the port select input, PS, is in a low state. This interface is

controlled by the signals

RST

, DIN, DOUT, CLK, and R/

. Timing diagrams for the 5-wire serial port

can be found in Figure 3. Timing information for the 5-wire serial port is provided in the AC Electrical

Characteristics table for 5-wire serial communications.

Data is loaded MSB first and in multiples of 8 bits. The 8-bit data to specify wiper position has the format

or protocol as that shown in Figure 2. The 8-bit data is divided into potentiometer select data and wiper

position value. The 6 least significant bits of data specify the wiper position value while the 2 most

significant bits specify the potentiometer to be loaded. This allows the interface control logic/protocol to

provide order independent potentiometer loading, as well as variable-length data loads.

As stated earlier, the 5-wire serial port is selected when the PS input is in a low state. If the device will

only be used in the 5-wire mode, the PS input can be tied directly to ground. Communication via the 5-

wire interface is enabled when

RST

is in a high state. A low-to-high transition on the

RST

indicates the

start of a communication transaction with the DS1844. While

RST

is high, data can be read or written to

the part. Data will be read or written dependent on the state of the read-write enable input, R/

. The

state of R/

must be stable before a low-to-high transition on

RST

. Once the

RST

input has begun a

communication transaction, the serial port will ignore any transitions on the R/

input.

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DS1844

When

writing

data, the R/

input should be in a

low state.

Once

RST

has activated the port, a data bit is

latched (or valid) on the low-to-high transition of the CLK signal. Once, eight low-to-high transitions

have occurred on the CLK input, the associated 8-bit data block will be loaded as the wiper’s value on the

falling edge of the eighth clock pulse. Potentiometer wiper values can be loaded in any order. Also,

potentiometer wiper data can be loaded 1, 2, 3, or 4 bytes at a time. When

RST

transitions from high to

low, the 5-wire port will be disabled.

While

RST

is high and R/

is low, (the write or load state) the cascade data output, D

OUT

will be

inhibited; preventing the passing of data from D

to D

OUT

. However, when

RST

is low data is passed

directly from D

to D

OUT

When

reading

data, the R/

input should be in a high state. Once

RST

has enabled the port, data can be

clocked out of the device and will appear on the D

OUT

terminal. A data bit will be valid on the falling

edge of a clock pulse after a maximum time period of 20 ns (of that falling edge). Data will appear on

OUT

most significant bit (MSB) first and starting with potentiometer-0, followed by potentiometer-1 and

so forth.

2-Wire Addressable Serial Port Control

The 2-wire serial port interface supports a bi-directional data transmission protocol with device

addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as

a receiver. The device that controls the message is called a “master.” The devices that are controlled by

the master are “slaves.” The bus must be controlled by a master device which generates the serial clock

(SCL), controls the bus access, and generates the START and STOP conditions. The DS1844 operates as

a slave on the two-wire bus. Connections to the bus are made via the open-drain I/O lines SDA and SCL.

The 2-wire serial port is selected when the port select input, PS, is in a high-state. The following I/O

terminals control the 2-wire serial port: SDA, SCL, A0, A1, A2, PS=1. Timing diagrams for the 2-wire

serial port can be found in Figures 4 through 8. Timing information for the 2-wire serial port is provided

in the AC Electrical Characteristics table for 2-wire serial communications.

The following bus protocol has been defined (See Figure 4).

Data transfer may be initiated only when the bus is not busy.

During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes

in the data line while the clock line is high will be interpreted as control signals.

Accordingly, the following bus conditions have been defined:

Bus not busy:

Both data and clock lines remain HIGH.

Start data transfer:

A change in the state of the data line from HIGH to LOW while the clock is HIGH

defines a START condition.

Stop data transfer:

A change in the state of the data line from LOW to HIGH while the clock line is

HIGH defines the STOP condition.

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DS1844

Data valid:

The state of the data line represents valid data when, after a START condition, the data line

is stable for the duration of the HIGH period of the clock signal. The data on the line can be changed

during the LOW period of the clock signal. There is one clock pulse per bit of data. Figure 4 details how

data transfer is accomplished on the two-wire bus. Depending upon the state of the R/W bit, two types of

data transfer are possible.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The

number of data bytes transferred between START and STOP conditions is not limited and is determined

by the master device. The information is transferred byte-wise and each receiver acknowledges with a 9

bit.

Within the bus specifications a regular mode (100 kHz clock rate) and a fast mode (400 kHz clock rate)

are defined. The DS1844 works in both modes.

Acknowledge:

Each receiving device, when addressed, is obliged to generate an acknowledge after the

reception of each byte. The master device must generate an extra clock pulse which is associated with this

acknowledge bit.

A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into account. A master must signal an end of data to the slave

by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,

the slave must leave the data line HIGH to enable the master to generate the STOP condition.

Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master

is the command/control byte. Next follows a number of data bytes. The slave returns an

acknowledge bit after each received byte.

Data transfer from a slave transmitter to a master receiver. The 1

byte (the command/control

byte) is transmitted by the master. The slave then returns an acknowledge bit. Next follows a

number of data bytes transmitted by the slave to the master. The master returns an acknowledge

bit after all received bytes other than the last byte. At the end of the last received byte, a ‘not

acknowledge’ can be returned.

The master device generates all serial clock pulses and the START and STOP conditions. A transfer is

ended with a STOP condition or with a repeated START condition. Since a repeated START condition is

also the beginning of the next serial transfer, the bus will not be released.

The DS1844 may operate in the following two modes:

Slave receiver mode: Serial data and clock are received through SDA and SCL, respectively. After

each byte is received, an acknowledge bit is transmitted. START and STOP conditions are

recognized as the beginning and end of a serial transfer. Address recognition is performed by

hardware after reception of the slave (device) address and direction bit.

Slave transmitter mode: The 1

byte is received and handled as in the slave receiver mode.

However, in this mode the direction bit will indicate that the transfer direction is reversed. Serial

data is transmitted on SDA by the DS1844 while the serial clock is input on SCL. START and

STOP conditions are recognized as the beginning and end of a serial transfer.

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DS1844

A command/control byte is the 1

byte received following the START condition from the master device.

The command/control byte consists of a 4-bit control code. For the DS1844, this is set as

0101

binary for

read/write operations. The next 3 bits of the command/ control byte are the device select bits or slave

address (A2, A1, A0). They are used by the master device to select which of eight devices is to be

accessed. When reading or writing the DS1844, the device-select bits must match the device-select pins

(A2, A1, A0). The last bit of the command/control byte (R/W) defines the operation to be performed.

When set to a 1 a read operation is selected, and when set to a 0 a write operation is selected. Figure 5

shows the command/control byte structure for the DS1844.

Following the START condition, the DS1844 monitors the SDA bus checking the device type identifier

being transmitted. Upon receiving the 0101 control code, the appropriate device address bits, and the

read/write bit, the slave device outputs an acknowledge signal on the SDA line.

SLAVE ADDRESS

COMMAND AND PROTOCOL

The command and protocol structure of the DS1844 allows the user to read or write the potentiometer(s).

Additionally, the 2-wire command/protocol structure of the DS1844 will support eight different devices

and a maximum of 32 channels that can be uniquely controlled. The command structures for the device

are presented in Figures 6 and 7. Potentiometer data values and control and command values are always

transmitted most significant bit (MSB) first. During communications, the receiving unit always generates

the acknowledgement.

Reading the DS1844

As shown in Figure 6, the DS1844 provides one

read command operation.

This operation allows the user

to read all potentiometers. Specifically, the R/W bit of the command/control byte is set equal to a 1 for a

read operation. Communication to read the DS1844 begins with a START condition which is issued by

the master device. The command/control byte from the master device will follow the START condition.

Once the command/control byte has been received by the DS1844, the part will respond with an

ACKNOWLEDGE. The read/write bit of the command/control byte, as stated, should be set equal to 1

for reading the DS1844.

When the master has received the ACKNOWLEDGE from the DS1844, the master can then begin to

receive potentiometer wiper data. The value of the potentiometer-0 wiper position will be the first

returned from the DS1844, followed by potentiometer-1 and so forth. Once the 8 bits of the

potentiometer-0 wiper position have been transmitted, the master will need to issue an

ACKNOWLEDGE, unless it is the only byte to be read, in which case the master issues a NOT

ACKNOWLEDGE. If desired the master may stop the communication transfer at this point by issuing the

STOP condition. However, if the value of the remaining potentiometers is needed, transfer can continue

by clocking the 8 bits of the potentiometer-1 value, followed by an ACKNOWLEDGE, and so forth.

Final communication transfer is terminated by issuing the STOP command. Again, the flow of the read

operation is presented in Figure 6.

Writing the DS1844

A data flow diagram for writing the DS1844 is shown in Figure 7. The DS1844 has one write command

that is used to change the position(s) of the wiper. The 2-wire serial interface write structure is similar to

that of the 5-wire serial write. However, there are differences.

All the write operations begin with a START condition. Following the START condition, the master

device will issue the command/control byte. The read/write bit of the command/control byte will be set to

5 of 14

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