21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74FCT163373
3.3V 16-BIT TRANSPARENT LATCH
PI74FCT163373
Fast CMOS 3.3V 16-Bit
Transparent Latch
Product Features
• Advanced Low Power CMOS Operation
• Can serve as a 5V to 3V translator
• Excellent output drive capability:
Balanced drives (24mA sink and source)
Compatible with LVC
TM
class of products.
• Pin compatible with industry standard
double-density pinouts
• Low ground bounce outputs
• Hysteresis on all inputs
• Industrial operating temperature range: –40°C to +85°C
• Inputs can be driven by 3.3V or 5V devices
• Multiple center pin and distributed Vcc/GND pins
minimizing switching noise
• Packages available:
– 48-pin 240 mil wide plastic TSSOP (A)
– 48-pin 300 mil wide plastic SSOP (V)
– 48-pin 173 mil wide plastic TVSOP (K)
• Device models available on request
Product Description
Pericom Semiconductor’s PI74FCT series of logic circuits are
produced in the Company’s advanced 0.6 micron CMOS
technology, achieving industry leading speed grades.
The PI74FCT163373 is a 16-bit transparent latch designed with
3-state outputs and are intended for bus oriented applications. The
Output Enable and Latch Enable controls are organized to operate
as two 8-bit latches or one 16-bit latch. When Latch Enable (LE)
is HIGH, the flip-flops appear transparent to the data. The data that
meets the set-up time when LE is LOW is latched. When OE is
HIGH, the bus output is in the high impedance state.
Logic Block Diagram
1
OE
2
OE
1
LE
2
LE
1
D
0
D
1
O
0
2
D
0
D
2
O
0
C
C
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
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Product Pin Configuration
1
OE
1
O
0
1
O
1
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74FCT163373
3.3V 16-BIT TRANSPARENT LATCH
Product Pin Description
Pin Name
xOE
xLE
xDx
xOx
GND
V
CC
Description
3-State Output Enable Inputs (Active LOW)
Latch Enable Inputs (Active HIGH)
Data Inputs
3-State Outputs
Ground
Power
Truth Table
xDx
H
L
X
Inputs
(1)
xLE
H
H
X
xOE
L
L
H
Outputs
(1)
xOx
H
L
Z
Note:
1. H = High Voltage Level, X = Don’t Care,
L = Low Voltage Level, Z = High Impedance
1
2
3
4
5
6
7
48
47
46
45
44
43
42
1
LE
1
D
0
1
D
1
GND
1
O
2
1
O
3
GND
1
D
2
1
D
3
V
CC
1
O
4
1
O
5
GND
1
O
6
1
O
7
2
O
0
2
O
1
8
41
9
48-PIN
40
10
39
V48
A48
11
38
K48
12
37
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
30
29
28
27
26
25
V
CC
1
D
4
1
D
5
GND
1
D
6
1
D
7
2
D
0
2
D
1
GND
2
O
2
2
O
3
GND
2
D
2
2
D
3
V
CC
2
O
4
2
O
5
V
CC
2
D
4
2
D
5
GND
2
O
6
2
O
7
2
OE
GND
2
D
6
2
D
7
2
LE
Capacitance
(T
A
= 25°C, f = 1 MHz)
Parameters
(1)
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
4.5
5.5
Max.
6
8
Units
pF
pF
Note:
1. This parameter is determined by device characterization but is not production tested.
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PI74FCT163373
3.3V 16-BIT TRANSPARENT LATCH
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ......................................................... –55°C to +125°C
Ambient Temperature with Power Applied ........................ –40°C to +85°C
Supply Voltage to Ground Potential (Inputs & Vcc Only) .. –0.5V to +7.0V
Supply Voltage to Ground Potential (Outputs & D/O Only) –0.5V to +7.0V
DC Input Voltage ................................................................. –0.5V to +7.0V
DC Output Current ........................................................................... 120 mA
Power Dissipation ................................................................................. 1.0W
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the de-
vice. This is a stress rating only and functional opera-
tion of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
DC Electrical Characteristics
(Over the Operating Range, T
A
= –40°C to +85°C, V
CC
= 2.7V to 3.6V)
Parameters
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
I
ODH
I
ODL
V
OH
Description
Input HIGH Voltage (Input pins)
Input HIGH Voltage (I/O pins)
Input LOW Voltage
(Input and I/O pins)
Input HIGH Current (Input pins)
Input HIGH Current (I/O pins)
Input LOW Current (Input pins)
Input LOW Current (I/O pins)
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Output HIGH Current
Output LOW Current
Output HIGH Voltage
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
Min.
2.2
2.0
–0.5
Typ
(2)
—
—
—
—
—
—
—
—
—
–0.7
–60
90
—
3.0
3.0
—
—
0.2
0.3
–60
Max.
5.5
Vcc+0.5
0.8
±1
±1
±1
±1
±1
±1
–1.2
–110
200
—
—
—
—
0.2
0.4
0.5
–85
Units
V
V
V
µA
µA
µA
µA
µA
µA
V
mA
mA
V
V
V
V
V
V
V
–240
V
OL
Output LOW Voltage
I
OS
Short Circuit Current
(4)
mA
V
H
Input Hysteresis
—
150
—
mV
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. V
OH
= V
CC
– 0.6V at rated current.
V
CC
= Max.
V
IN
= 5.5V
—
V
CC
= Max.
V
IN
= V
CC
—
V
CC
= Max.
V
IN
= GND
—
V
CC
= Max.
V
IN
= GND
—
V
CC
= Max.
V
OUT
= V
CC
—
V
CC
= Max.
V
OUT
= GND
—
V
CC
= Min., I
IN
= –18 mA
—
(3)
V
CC
= 3.3V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
–36
(3)
V
CC
= 3.3V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
50
V
CC
= Min.
I
OH
= –0.1mA Vcc-0.2
V
IN
= V
IH
or V
IL
I
OH
= –3mA
2.4
V
CC
= 3.0V,
I
OH
= –8mA
2.4
(5)
V
IN
= V
IH OR
V
IL
I
OH
= –24mA
2.0
V
CC
= Min.
I
OL
= 0.1mA
—
V
IN
= V
IH
or V
IL
I
OL
= 16mA
—
I
OL
= 24mA
—
(3)
, V
OUT
= GND
V
CC
= Max.
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PS2055B
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PI74FCT163373
3.3V 16-BIT TRANSPARENT LATCH
Power Supply Characteristics
Parameters Description
I
CC
∆I
CC
I
CCD
Quiescent Power Supply Current
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
(4)
Test Conditions
(1)
V
CC
= Max.
V
CC
= Max.
V
CC
= Max.,
Outputs Open
X
OE = GND
xLE = Vcc
One Bit Toggling
50% Duty Cycle
V
CC
= Max.,
Outputs Open
f
I
= 10 MH
Z
50% Duty Cycle
X
OE = GND
X
LE = V
CC
One Bit Toggling
V
CC
= Max.,
Outputs Open
f
I
= 2.5 MH
Z
50% Duty Cycle
X
OE = GND
X
LE = V
CC
16 Bits Toggling
V
IN
= GND or V
CC
V
IN
= V
CC
– 0.6V
(3)
V
IN
= V
CC
V
IN
= GND
Min.
Typ
(2)
0.1
2.0
50
Max.
10
30
75
Units
µA
µA
µA/
MHz
I
C
Total Power Supply
Current
(6)
V
IN
= V
CC
– 0.6V
V
IN
= GND
0.5
0.8
mA
V
IN
= V
CC
– 0.6V
V
IN
= GND
2.0
3.3
(5)
Notes:
1. For Max. or Min.conditions, use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at Vcc = 3.3V, +25°C ambient.
3. Per TTL driven input; all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. I
C
=I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
I
N
I
)
I
CC
= Quiescent Current (I
CCL
, I
CCH
and I
CCZ
)
∆I
CC
= Power Supply Current for a TTL High Input
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
f
I
= Input Frequency
N
I
= Number of Inputs at f
I
All currents are in milliamps and all frequencies are in megahertz.
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PI74FCT163373
3.3V 16-BIT TRANSPARENT LATCH
Switching Characteristics over Operating Range
(1)
FCT163373
Com.
Parameters
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
W
t
SK
(o)
Description
Propagation Delay
xDx to xOx
Propagation Delay
xLE to xOx
Output Enable Time
xOE to xOx
Output Disable Time
(4)
xOE to xOx
Setup Time HIGH
or LOW, xDx to xLE
Hold Time HIGH
or LOW, xDx to xLE
xLE Pulse Width
HIGH
Output Skew
(5)
Conditions
(2)
C
L
= 50 pF
R
L
= 500
Ω
Min.
(3)
1.5
2.0
1.5
1.5
2.0
1.5
6.0
0.5
Max.
8.0
13.0
12.0
7.5
1.5
2.0
1.5
1.5
2.0
1.5
5.0
0.5
FCT163373A
Com.
Min.
(3)
Max.
5.2
8.5
6.5
5.5
1.5
2.0
1.5
1.5
2.0
1.5
5.0
0.5
FCT163373C
Com.
Min.
(3)
Max.
4.2
5.5
5.5
5.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Propagation Delays and Enable/Disable times are with Vcc = 3.3V ±0.3V, normal range. For Vcc = 2.7V, extended range,
all Propagation Delays and Enable/Disable times should be degraded by 20%.
2. See test circuit and wave forms.
3. Minimum limits are guaranteed but not tested on Propagation Delays.
4. This parameter is guaranteed but not production tested.
5. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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