UNISONIC TECHNOLOGIES CO., LTD
4066
QUAD BILATERAL SWITCH
DESCRIPTION
The UTC
4066
is a quad bilateral switch intended for the
transmission or multiplexing of analog or digital signals.
SOP-14
CMOS IC
FEATURES
* Wide supply voltage range: 3V ~ 15V.
* High noise immunity : 0.45V
DD
(typ.)
* Wide range of digital and ± 7.5V
PEAK
analog switching
* “ON” resistance for 15V operation : 80Ω
* Matched ”ON” resistance :
△
R
ON
=5Ω (typ.)
over 15V signal input
* “ON” resistance flat over peak-to-peak signal range
* High “ON” / “OFF” : 65 dB (typ.)
output voltage ratio @ f
IS
=10kHz, R
L
=10kΩ
* High degree linearity: 0.1% distortion (typ.).
@ f
IS
=1kHz, V
IS
=5Vp-p.
*
V
DD
-V
SS
=10V, R
L
=10kΩ
* Extremely low ”OFF” : 0.1nA (typ.)
*
switch leakage @V
DD
-V
SS
=10V, Ta=25℃
* Extremely high control input impedance : 10
12
Ω
(typ.)
* Low crosstalk : -50dB (typ.)
*
between switches @ f
IS
=0.9MHz, R
L
=1kΩ
* Frequency response, switch ”ON” : 40MHz (typ.)
DIP-14
TSSOP-14
*Pb-free plating product number: 4066L
ORDERING INFORMATION
Ordering Number
Normal
Lead Free Plating
4066-D14-T
4066L-D14-T
4066-S14-R
4066L-S14-R
4066-S14-T
4066L-S14-T
4066-P14-R
4066L-P14-R
4066-P14-T
4066L-P14-T
Package
DIP-14
SOP-14
SOP-14
TSSOP-14
TSSOP-14
Packing
Tube
Tape Reel
Tube
Tape Reel
Tube
4066L-D14-T
(1)Packing Type
(2)Package Type
(3)Lead Plating
(1) R: Tape Reel, T: Tube
(2) D14: DIP-14, S14: SOP-14, P14: TSSOP-14
(3) L: Lead Free Plating Blank: Pb/Sn
,
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QW-R502-009,C
4066
PIN CONFIGURATION
1
2
3
SW D
14 V
DD
13 CONTROL A
12 CONTROL D
11 IN/ OUT
10 OUT/ IN
9
SW C
8
OUT / IN
IN / OUT
CMOS IC
IN / OUT
OUT/ IN
OUT/ IN
SW A
IN / OUT 4
CONTROL B 5
CONTROL C 6
Vss 7
SW B
SCHEMATIC DIAGRAM
IN/ OUT
OUT/ IN
CONTROL
Vss
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QW-R502-009,C
4066
ABSOLUTE MAXIMUM RATINGS
(V
SS
=0V, unless otherwise specified)
PARAMETER
SYMBOL
V
DD
V
IN
CMOS IC
RATINGS
UNIT
Supply Voltage
-0.5 ~ +18
V
Input Voltage
-0.5 ~ Vcc+0.5
V
700
DIP-14
mW
Power Dissipation
P
D
SOP-14
500
mW
TSSOP-14
500
mW
Junction Temperature
T
J
+125
°C
Storage Temperature
T
STG
-40 ~ +150
°C
Note Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
RECOMMENDED OPERATING CONDITIONS
(V
SS
=0V, unless otherwise specified)
PARAMETER
Supply Voltage
Input Voltage
Operating Temperature Range
SYMBOL
V
DD
V
IN
T
OPR
RATINGS
3 ~ 15
0 ~ V
DD
-40 ~ +85
UNIT
V
V
°C
DC ELECTRICAL CHARACTERISTICS
(V
SS
=0V, unless otherwise specified)
PARAMETER
Quiescent
Current
Device
SYMBOL
CONDITIONS
-40°C
MIN MAX
1.0
2.0
4.0
MIN
+25°C
TYP
0.01
0.01
0.01
MAX
1.0
2.0
4.0
+85°C
UNITS
MIN
MAX
µA
7.5
µA
15
µA
30
V
DD
=5V
I
DD
V
DD
=10V
V
DD
=15V
SIGNAL INPUTS AND OUTPUTS
Input or Output
Leakage
I
IS
Vc=0
Switch “OFF”
R
L
=10kΩ ~ (V
DD
-V
SS
/2)
Vc=V
DD
, V
SS
~ V
DD
V
DD
=5V
“ON” Resistance
R
ON
V
DD
=10V
V
DD
=15V
R
L
=10kΩ ~ (V
DD
-V
SS
/2)
△
”ON” Resistance
Vc=V
DD
, V
IS
=V
SS
~V
DD
Between Any 2 of 4
△
R
ON
V
DD
=10V
Switches
V
DD
=15V
CONTROL INPUTS
V
IS
= V
SS
and V
DD
Vos=V
DD
and V
SS
I
IS
= ±10µA
Low Level Input
V
ILC
Voltage
V
DD
=5V
V
DD
=10V
V
DD
=15V
V
DD
=5V
HIGH Level Input
V
IHC
V
DD
=10V (Note 4)
Voltage
V
DD
=15V
V
DD
-V
SS
=15V
V
DD
≧V
IS
≧V
SS
Input Current
I
IN
V
DD
≧Vc≧V
SS
±50
±0.1
±50
±200
nA
850
330
210
270
120
80
1050
400
240
1200
520
300
Ω
Ω
Ω
10
5
Ω
Ω
1.5
3.0
4.0
3.5
7.0
11.0
±0.3
3.5
7.0
11.0
2.25
4.5
6.75
2.75
5.5
8.25
±10
-5
1.5
3.0
4.0
3.5
7.0
11.0
±0.3
1.5
3.0
4.0
V
V
V
V
V
V
µA
±1.0
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QW-R502-009,C
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(Ta=25
℃
, tr=tf=20 ns and Vss=0V unless otherwise)
PARAMETER
SYMBOL
Propagation Delay Time Signal
Input to Signal Output
Propagation Delay Time
Control Input to Signal
Output High Impedance to
Logical Level
Propagation Delay Time
Control Input to Signal
Output Logical Level to
High Impedance
Sine Wave Distortion
Frequency Response -Switch
“ON” (Frequency at-3dB)
T
PHL
, T
PLH
CONDITIONS
MIN
TYP
25
15
10
CMOS IC
AC ELECTRICAL CHARACTERISTICS
(AC Parameters are guaranteed by DC correlated testing)
MAX UNITS
55
ns
35
25
125
60
50
125
60
50
0.1
40
ns
ns
ns
ns
ns
ns
ns
ns
%
MHz
t
PZH
, t
PLZ
V
DD
=5V
Vc=V
DD
, C
L
=50pF, (Figure1)
V
DD
=10V
R
L
=200k
V
DD
=15V
R
L
=1.0kΩ, C
L
=50pF
V
DD
=5V
(Figure 2, Figure3)
V
DD
=10V
V
DD
=15V
R
L
=1.0kΩ, C
L
=50pF, (Figure 2, Figure3)
V
DD
=5V
V
DD
=10V
V
DD
=15V
Vc=V
DD
=5V, Vss= -5V
R
L
=10kΩ, V
IS
=5V
P-P
, f=1kHz, (Figure 4)
Vc=V
DD
=5V, Vss= -5V
R
L
=1kΩ, V
IS
=5Vp-p
20 Log10 V
OS
/V
OS
(1kHz)-dB
(Figure 4)
V
DD
=5.0V, Vcc=Vss= -5.0V,
R
L
=1kΩ, V
IS
=5.0V
P-P
, 20Log
10
,
V
OS
/V
IS
= -50dB, (Figure 4)
V
DD
=V
C
(A)=5.0V; Vss=Vc (B)=5.0V,
R
L
=1kΩ, V
IS
(A)=5.0V
P-P
, 20Log
10
,
V
OS
(B)/V
IS
(A)= -50dB (Figure 5)
V
DD
=10V, R
L
=10kΩ, R
IN
=1.0kΩ
Vcc=10V Square Wave, C
L
=50pF
(Figure 6)
R
L
=1.0kΩ, C
L
=50pF, (Figure 7)
Vos (f) =1/2Vos (1.0kHz)
V
DD
=5.0V
V
DD
=10V
V
DD
=15V
V
DD
=10V
V
C
=0V
t
PHZ
, t
PLZ
Feedthrough - Switch “OFF”
(Frequency at –50 dB)
Crosstalk Between Any Two
Switches(Frequency at-50dB)
Crosstalk; Control Input to
Signal Output
Maximum Control Input
1.25
0.9
MHz
150
mV
p-p
Signal Input Capacitance
Signal Output Capacitance
Feedthrough Capacitance
Control lnput Capacitance
C
IS
C
OS
C
IOS
C
IN
6.0
8.0
8.5
8.0
8.0
0.5
5.0
7.5
MHz
MHz
MHz
pF
pF
pF
pF
Note 1: These devices should not be connected to circuits with the power ”ON”
Note 2: In all cases, these is approximately 5pF of probe and jig capacitance in the output; however, this capacitance
is included in C
L
wherever it is specified.
Note 3: V
IS
is the voltage at the in/out pin and V
OS
is the voltage at the out/in pin. Vc is the voltage at the control
input.
Note 4: Conditions for V
IHC
: (a) V
IS
=V
DD
, Ios=standard B series I
OH
. (b) V
IS
=0V, I
OL
=standard B series I
OL
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QW-R502-009,C
4066
SPECIAL CONSIDERATIONS
CMOS IC
In applications where separate power sources are used to drive V
DD
and the signal input, the V
DD
current capability
should exceed V
DD
/R
L
(R
L
=effective external load of the UTC
4066
bilateral switches).This provision avoids any
permanent current flow or clamp action of the V
DD
supply when power is applied or removed from UTC 4066.
In certain applications, the external load-resistor current may include both V
DD
and Signal-line components. To
avoid drawing V
DD
current when switch current flows into terminals 1,4,8 or 11,the voltage drop across the
bidirectional swith must not exceed 0.6V at Ta
≤
25
℃
, or 0.4V at Ta >25℃ (calculated from R
ON
values shown).
NO V
DD
current will flow through R
L
if the switch current flows into terminals2, 3, 9 or 10.
AC TEST CIRCUITS AND SWITCHING TIME WAVEFORMS
V
C
=V
DD
V
DD
CONTROL
V
DD
1 OF 4 OU
OUT/IN
/IN
IN/OUT
T
SWITCHES
Vss
V
DD
V
IS
V
OS
C
L
50 pF
R
L
200 KΩ
V
OS
0V
0V
V
DD
50%
tf
90%
50%
10%
tf
V
IS
t
PLN
t
PNL
FIGURE 1. t
PHL
, t
PLH
Propagation Delay Time Signal Input to Signal Output
V
C
V
DD
V
DD
CONTROL
1 OF 4
IN/OUT
OUT/IN
SWITCHES
Vss
C
L
50pF
V
DD
t
PZH
V
DD
50%
V
OS
R
L
1KΩ
0V
V
OH
0V
t
PZH
10%
0V
V
OH
0V
t
PHZ
50%
t
PHZ
90%
V
DD
V
IS
=V
DD
FIGURE 2. t
PZH
, t
PHZ
Propagation Delay Time Control to Signal Output
V
C
V
DD
V
DD
CONTROL
1OF 4
OUT/IN
IN/OUT
SWITCHES
Vss
V
DD
R
L
1KΩ
V
OS
C
L
50pF
t
PZL
V
DD
50%
0V
V
DD
V
OL
t
PZL
90%
0V
V
DD
V
OL
10%
V
DD
t
PLZ
50%
t
PLZ
V
IS
=0V
FIGURE 3 . t
PZL
, t
PLZ
Propagation Delay Time Control to Signal Output
V
C
5V
CONTROL
V
DD
1OF 4
IN/OUT
OUT/IN
SWITCHES
Vss
2.5V
V
OS
R
L
V
IS
= 0V
-2.5V
1 /f
V
IS
-5V
Vc=V
DD
for distortion and frequency response tests
Vc= Vss for feedthrough test
FIGURE 4. Sine Wave Distortion, Frequency Response and Feedthrough
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QW-R502-009,C
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