Integrated
Circuit
Systems, Inc.
ICS85301
2:1
D
IFFERENTIAL
-
TO
-LVPECL M
ULTIPLEXER
F
EATURES
•
2:1 LVPECL MUX
•
One LVPECL output
•
Two differential clock inputs can accept: LVPECL, LVDS,
CML
•
Maximum input/output frequency: 3GHz
•
Translates LVCMOS/LVTTL input signals to LVPECL levels
by using a resistor bias network on nPCLK0, nPCLK0
•
Propagation delay: 490ps (maximum)
•
Part-to-part skew: 150ps (maximum)
•
Additive phase jitter, RMS: 0.009ps (typical)
•
Full 3.3V or 2.5V operating supply
•
-40°C to 85°C ambient operating temperature
•
Available in both standard and lead-free RoHS compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS85301 is a high performance 2:1 Differ-
ential-to-LVPECL Multiplexer and a member of the
HiPerClockS™
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS85301 can also per-
form differential translation because the differ-
ential inputs accept LVPECL, CML as well as LVDS levels.
The ICS85301 is packaged in a small 3mm x 3mm
16 VFQFN package, making it ideal for use on space con-
strained boards.
IC
S
B
LOCK
D
IAGRAM
PCLK0
nPCLK0
PCLK1
nPCLK1
0
Q
nQ
1
P
IN
A
SSIGNMENT
PCLK0 1
nPCLK0 2
PCLK1 3
nPCLK1 4
5
V
BB
16 15 14 13
12
11
10
9
6
CLK_SEL
V
CC
V
EE
V
EE
nc
V
EE
Q
nQ
V
EE
7
nc
8
V
CC
CLK_SEL
V
BB
ICS85301
16-Lead VFQFN
3mm x 3mm x 0.95 package body
K Package
Top View
PCLK0
nPCLK0
PCLK1
nPCLK1
V
BB
CLK_SEL
nc
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
nc
V
EE
V
EE
V
CC
V
EE
Q
nQ
V
EE
ICS85301
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
85301AK
www.icst.com/products/hiperclocks.html
1
REV. A JANUARY 16, 2006
Integrated
Circuit
Systems, Inc.
ICS85301
2:1
D
IFFERENTIAL
-
TO
-LVPECL M
ULTIPLEXER
Type
Description
Non-inver ting differential LVPECL clock input.
Inver ting differential LVPECL clock input. V
CC
/2 default when left floating.
Non-inver ting differential LVPECL clock input.
Inver ting differential LVPECL clock input. V
CC
/2 default when left floating.
Bias voltage.
No connect.
Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs.
When LOW, selects PCLK0, nPCLK0 inputs.
LVCMOS / LVTTL interface levels.
Positive supply pins.
Negative supply pins.
Differential output pair. LVPECL interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
7, 16
6
8, 13
9, 12, 14, 15
10, 11
Name
PCLK0
nPCLK0
PCLK1
nPCLK1
V
BB
nc
CLK_SEL
V
CC
V
EE
nQ, Q
Input
Input
Input
Input
Output
Unused
Input
Power
Power
Output
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
1
37
37
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Input
CLK_SEL
0
1
Input Selected
PCLK
PCLK0, nPCLK0
PCLK1, nPCLK1
85301AK
www.icst.com/products/hiperclocks.html
2
REV. A JANUARY 16, 2006
Integrated
Circuit
Systems, Inc.
ICS85301
2:1
D
IFFERENTIAL
-
TO
-LVPECL M
ULTIPLEXER
4.6V
-0.5V to V
CC
+ 0.5 V
50mA
100mA
51.5°C/W (0 lfpm)
89°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
16 VFQFN
16 TSSOP
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V ± 5%, T
A
= -40°C
TO
85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
26
Units
V
mA
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 2.5V ± 5%, T
A
= -40°C
TO
85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
24
Units
V
mA
T
ABLE
4C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V ± 5%
OR
2.5V ± 5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK_SEL
CLK_SEL
CLK_SEL
CLK_SEL
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
Units
V
V
µA
µA
NOTE: Outputs terminated with 50
Ω
to V
CC
/2. See Parameter Measurement Information, "Output Load Test Circuit".
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V ± 5%, T
A
= -40°C
TO
85°C
Symbol Parameter
I
IH
I
IL
V
PP
V
CMR
V
OH
V
OL
V
BB
Input High Current
Input Low Current
PCLK0, nPCLK0,
PCLK1, nPCLK1
PCLK0, PCLK1
nPCLK0, nPCLK1
Test Conditions
V
CC
= V
IN
= 3.465
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-10
-150
150
1.2
2.01
1.24
1.695
1200
3.3
2.535
1.845
2.145
Minimum
Typical
Maximum
150
Units
µA
µA
µA
mV
V
V
V
V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
Output High Voltage; NOTE 3
Output Low Voltage; NOTE 3
Bias Voltage
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications
,
the maximum input voltage for PCLKx, nPCLKx is V
CC
+ 0.3V.
NOTE 3: Outputs terminated with 50
Ω
to V
CC
- 2V. .
85301AK
www.icst.com/products/hiperclocks.html
3
REV. A JANUARY 16, 2006
Integrated
Circuit
Systems, Inc.
ICS85301
2:1
D
IFFERENTIAL
-
TO
-LVPECL M
ULTIPLEXER
Test Conditions
PCLK0, nPCLK0,
PCLK1, nPCLK1
PCLK0, PCLK1
nPCLK0, nPCLK1
V
CC
= V
IN
= 2.625V
V
CC
= 2.625V, V
IN
= 0V
V
CC
= 2.625V, V
IN
= 0V
-10
-150
150
1.2
1.25
0.48
0.935
1200
2.5
1.705
1.005
1.305
Minimum
Typical
Maximum
150
Units
µA
µA
µA
mV
V
V
V
V
T
ABLE
4E. LVPECL DC C
HARACTERISTICS
,
V
CC
= 2.5V ± 5%, T
A
= -40°C
TO
85°C
Symbol Parameter
Input High
I
IH
Current
I
IL
V
PP
V
CMR
V
OH
V
OL
V
BB
Input Low Current
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
Output High Voltage; NOTE 3
Output Low Voltage; NOTE 3
Bias Voltage
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications
,
the maximum input voltage for PCLKx, nPCLKx is V
CC
+ 0.3V.
NOTE 3: Outputs terminated with 50
Ω
to V
CC
- 2V. .
T
ABLE
5A. AC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
t
sk(pp)
t
sk(i)
t
j it
t
R
/ t
F
odc
MUX_
ISOL
Parameter
Output Frequency
Propagation Delay; NOTE 1
Par t-to-Par t Skew; NOTE 2, 3
Input Skew
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
Output Rise/Fall Time
Output Duty Cycle
MUX Isolation
f = 622MHz
622MHz (Integration Range:
12KHz - 20MHz)
20% to 80%
240
Test Conditions
Minimum
Typical
Maximum
3
490
150
25
0.009
100
48
-55
200
52
Units
GHz
ps
ps
ps
ps
ps
%
dB m
All parameters measured at f
≤
1.7GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
CC
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
t
sk(pp)
t
sk(i)
t
j it
t
R
/ t
F
odc
MUX_
ISOL
85301AK
Parameter
Output Frequency
Propagation Delay; NOTE 1
Par t-to-Par t Skew; NOTE 2, 3
Input Skew
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
Output Rise/Fall Time
Output Duty Cycle
MUX Isolation
Test Conditions
Minimum
240
Typical
Maximum
3
490
150
25
Units
GHz
ps
ps
ps
ps
622MHz (Integration Range:
12KHz - 20MHz)
20% to 80%
f = 622MHz
0.009
100
47
-55
200
53
ps
%
dBm
For notes, see Table 5A above.
www.icst.com/products/hiperclocks.html
4
REV. A JANUARY 16, 2006
Integrated
Circuit
Systems, Inc.
ICS85301
2:1
D
IFFERENTIAL
-
TO
-LVPECL M
ULTIPLEXER
A
DDITIVE
P
HASE
J
ITTER
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
-30
-40
-50
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter
3.3V or 2.5V @ 622MHz (12KHz to 20MHz)
= 0.009ps typical
SSB P
HASE
N
OISE
dBc/H
Z
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
85301AK
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5
REV. A JANUARY 16, 2006
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