3D7110
MONOLITHIC 10-TAP
FIXED DELAY LINE
(SERIES 3D7110)
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
PACKAGES
IN
N/C
O2
O4
O6
O8
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VDD
O1
O3
O5
O7
O9
O10
All-silicon, low-power CMOS technology
IN
1
14 VDD
TTL/CMOS compatible inputs and outputs
N/C
2
13 O1
Vapor phase, IR and wave solderable
O2
3
12 O3
Auto-insertable (DIP pkg.)
O4
4
11 O5
Low ground bounce noise
Leading- and trailing-edge accuracy
O6
5
10 O7
Delay range:
.75 through 80ns
O8
6
9 O9
Delay tolerance:
5% or 1ns
GND
7
8 O10
Temperature stability:
±3%
typical (0C-70C)
3D7110 DIP
Vdd stability:
±1%
typical (4.75V-5.25V)
3D7110G Gull-Wing
Minimum input pulse width:
15% of total delay
14-pin Gull-Wing and 16-pin SOIC
available as drop-in replacements
For mechanical dimensions, click
here
.
for hybrid delay lines
For package marking details, click
here
.
3D7110D SOIC
(150 Mil)
IN
N/C
N/C
O2
O4
O6
O8
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
N/C
O1
O3
O5
O7
O9
O10
3D7110S SOL
(300 Mil)
FUNCTIONAL DESCRIPTION
The 3D7110 10-Tap Delay Line product family consists of fixed-delay
CMOS integrated circuits. Each package contains a single delay line,
tapped and buffered at 10 points spaced uniformly in time. Tap-to-tap
(incremental) delay values can range from 0.75ns through 8.0ns. The
input is reproduced at the outputs without inversion, shifted in time as
per the user-specified dash number. The 3D7110 is TTL- and CMOS-
compatible, capable of driving ten 74LS-type loads, and features both
rising- and falling-edge accuracy.
The all-CMOS 3D7110 integrated circuit has been designed as a
reliable, economic alternative to hybrid TTL fixed delay lines. It is offered
in a standard 14-pin auto-insertable DIP and space saving surface
mount 14- and 16-pin SOIC packages.
PIN DESCRIPTIONS
IN
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
VDD
GND
Delay Line Input
Tap 1 Output (10%)
Tap 2 Output (20%)
Tap 3 Output (30%)
Tap 4 Output (40%)
Tap 5 Output (50%)
Tap 6 Output (60%)
Tap 7 Output (70%)
Tap 8 Output (80%)
Tap 9 Output (90%)
Tap 10 Output (100%)
+5 Volts
Ground
Doc #96005
12/2/96
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
3D7110
TABLE 1: PART NUMBER SPECIFICATIONS
PART NUMBER
DIP-14
SOIC-14
SOIC-16
3D7110
3D7110D 3D7110S
3D7110G
-.75
-.75
-.75
-1
-1
-1
-1.5
-1.5
-1.5
-2
-2
-2
-2.5
-2.5
-2.5
-4
-4
-4
-5
-5
-5
-8
-8
-8
TOLERANCES
TOTAL
TAP-TAP
DELAY
DELAY
(ns)
(ns)
6.75
±
1.0*
0.75
±
0.4
9.0
±
1.0*
1.0
±
0.5
13.5
±
1.0*
1.5
±
0.7
18.0
±
1.0*
2.0
±
0.8
22.5
±
1.1*
2.5
±
1.0
36.0
±
1.8*
4.0
±
1.3
50.0
±
2.5
5.0
±
1.5
80.0
±
4.0
8.0
±
1.5
Max
Operating
Frequency
28.4 MHz
23.8 MHz
18.0 MHz
14.5 MHz
18.2 MHz
8.33 MHz
6.67 MHz
4.17 MHz
INPUT RESTRICTIONS
Absolute
Min
Max
Operating
Oper. Freq.
Pulse Width
166.7 MHz
17.6 ns
166.7 MHz
21.0 ns
166.7 MHz
27.8 ns
166.7 MHz
34.5 ns
125.0 MHz
27.5 ns
133.3 MHz
60.0 ns
66.7 MHz
75.0 ns
41.7 MHz
120.0 ns
Absolute
Min
Oper. P.W.
3.00 ns
3.00 ns
3.00 ns
3.00 ns
4.00 ns
6.00 ns
7.50 ns
12.0 ns
* Total delay referenced to Tap1 output; Input-to-Tap1 = 5.0ns
±
1.0ns
NOTE: Any dash number between .75 and 8 not shown is also available.
1996
Data Delay Devices
Doc #96005
12/2/96
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
2
3D7110
APPLICATION NOTES
OPERATIONAL DESCRIPTION
The 3D7110 ten-tap delay line architecture is
shown in Figure 1. The delay line is composed
of a number of delay cells connected in series.
Each delay cell produces at its output a replica of
the signal present at its input, shifted in time.
The delay cells are matched and share the same
compensation signals, which minimizes tap-to-
tap delay deviations over temperature and supply
voltage variations.
To guarantee the
Table 1
delay accuracy for
input frequencies higher than the
Maximum
Operating Frequency,
the 3D7110 must be
tested at the user operating frequency.
Therefore, to facilitate production and device
identification,
the part number will include a
custom reference designator
identifying the
intended frequency of operation. The
programmed delay accuracy of the device is
guaranteed, therefore, only at the user specified
input frequency. Small input frequency variation
about the selected frequency will only marginally
impact the programmed delay accuracy, if at all.
Nevertheless, it is strongly recommended that
the engineering staff at DATA DELAY
DEVICES be consulted.
INPUT SIGNAL CHARACTERISTICS
The Frequency and/or Pulse Width (high or low)
of operation may adversely impact the specified
delay accuracy of the particular device. The
reasons for the dependency of the output delay
accuracy on the input signal characteristics are
varied and complex. Therefore a
Maximum
and
an
Absolute Maximum
operating input
frequency and a
Minimum
and an
Absolute
Minimum
operating pulse width have been
specified.
OPERATING PULSE WIDTH
The
Absolute Minimum Operating Pulse
Width
(high or low) specification, tabulated in
Table 1,
determines the smallest Pulse Width of
the delay line input signal that can be
reproduced, shifted in time at the device output,
with acceptable pulse width distortion.
The
Minimum Operating Pulse Width
(high or
low) specification determines the smallest Pulse
Width of the delay line input signal for which the
output delay accuracy tabulated in
Table 1
is
guaranteed.
To guarantee the
Table 1
delay accuracy for
input pulse width smaller than the
Minimum
Operating Pulse Width,
the 3D7110 must be
tested at the user operating pulse width.
Therefore, to facilitate production and device
identification, the
part number will include a
OPERATING FREQUENCY
The
Absolute Maximum Operating Frequency
specification, tabulated in
Table 1,
determines
the highest frequency of the delay line input
signal that can be reproduced, shifted in time at
the device output, with acceptable duty cycle
distortion.
The
Maximum Operating Frequency
specification determines the highest frequency of
the delay line input signal for which the output
delay accuracy is guaranteed.
IN
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
Temp & VDD
Compensation
VDD
Figure 1: 3D7110 Functional Diagram
GND
Doc #96005
12/2/96
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
3D7110
APPLICATION NOTES (CONT’D)
custom reference designator
identifying the
intended frequency and duty cycle of operation.
The programmed delay accuracy of the device is
guaranteed, therefore, only for the user specified
input characteristics. Small input pulse width
variation about the selected pulse width will only
marginally impact the programmed delay
accuracy, if at all.
Nevertheless, it is strongly
recommended that the engineering staff at
DATA DELAY DEVICES be consulted.
circuitry to minimize the delay variations induced
by fluctuations in power supply and/or
temperature.
The
thermal coefficient
is reduced to
600
PPM/C,
which is equivalent to a variation , over
the 0C-70C operating range, of
±3%
from the
room-temperature delay settings and/or
1.0ns,
whichever is greater. The
power supply
coefficient
is reduced, over the 4.75V-5.25V
operating range, to
±1%
of the delay settings at
the nominal 5.0VDC power supply and/or
1.5ns,
whichever is greater.
It is essential that the
power supply pin be adequately bypassed
and filtered. In addition, the power bus
should be of as low an impedance
construction as possible. Power planes are
preferred.
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D7110 programmable delay line
utilizes novel and innovative compensation
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
SYMBOL
V
DD
V
IN
I
IN
T
STRG
T
LEAD
MIN
-0.3
-0.3
-1.0
-55
MAX
7.0
V
DD
+0.3
1.0
150
300
UNITS
V
V
mA
C
C
NOTES
25C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
Static Supply Current*
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Current
Low Level Output Current
Output Rise & Fall Time
SYMBOL
I
DD
V
IH
V
IL
I
IH
I
IL
I
OH
I
OL
T
R
& T
F
MIN
2.0
0.8
1
1
-4.0
4.0
2
MAX
30
UNITS
mA
V
V
µA
µA
mA
mA
ns
NOTES
V
IH
= V
DD
V
IL
= 0V
V
DD
= 4.75V
V
OH
= 2.4V
V
DD
= 4.75V
V
OL
= 0.4V
C
LD
= 5 pf
*I
DD
(Dynamic) = 10 * C
LD
* V
DD
* F
where: C
LD
= Average capacitance load/tap (pf)
F = Input frequency (GHz)
Input Capacitance = 10 pf typical
Output Load Capacitance (C
LD
) = 25 pf max
Doc #96005
12/2/96
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
4
3D7110
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
Ambient Temperature:
25
o
C
±
3
o
C
Supply Voltage (Vcc):
5.0V
±
0.1V
Input Pulse:
High = 3.0V
±
0.1V
Low = 0.0V
±
0.1V
Source Impedance:
50Ω Max.
Rise/Fall Time:
3.0 ns Max. (measured
between 0.6V and 2.4V
)
Pulse Width:
PW
IN
= 1.25 x Total
Delay
Period:
PER
IN
= 2.5 x Total
Delay
OUTPUT:
R
load
:
C
load
:
Threshold:
10KΩ
±
10%
5pf
±
10%
1.5V (Rising & Falling)
Device
Under
Test
10KΩ
5pf
Digital
Scope
470Ω
COMPUTER
SYSTEM
PRINTER
PULSE
GENERATOR
OUT
TRIG
IN
DEVICE UNDER
TEST (DUT)
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
REF
IN
TRIG
DIGITAL SCOPE/
TIME INTERVAL COUNTER
Figure 2: Test Setup
NOTE:
The above conditions are for test only and do not in any way restrict the operation of the device.
PER
IN
PW
IN
t
RISE
INPUT
SIGNAL
2.4V
1.5V
0.6V
t
FALL
V
IH
2.4V
1.5V
0.6V
V
IL
t
PHL
t
PLH
OUTPUT
SIGNAL
1.5V
V
OH
1.5V
V
OL
Figure 3: Timing Diagram
Doc #96005
12/2/96
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5
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