22
23
24
27
26
25
GND
D13
D14
D1
V
REF
Q13
Q14
48
35
TO 13 OTHER CHANNELS
08-0291
1
V
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74SSTV16857
14-Bit Registered Buffer
Product Features
• PI74 SSTV16857 is designed for low-voltage operation,
V
DD
= V
DDQ
= 2.3V to 2.7V
• Supports SSTL_2 Class I and II specifications
• SSTL_2 Input and Output Levels
• Designed for DDR Memory
• Flow-Through Architecture
• Packaging:
– 48-pin, 240-mil wide plastic TSSOP (A)
– 48-pin, 240-mil wide Lead-Free plastic TSSOP (AE)
Product Description
Pericom Semiconductor’s PI74SSTV16857 series of logic circuits
are produced using the Company’s advanced 0.35 micron CMOS
technology, achieving industry leading speed.
The 14-bit PI74SSTV16857 universal bus driver is designed
for 2.3V to 2.7V V
DD
operation and SSTL_2 I/O Levels except for
the RESET input which is LVCMOS.
Data flow from D to Q is controlled by the differential clock , CLK,
CLK and RESET. Data is triggered on the positive edge of CLK.
CLK must be used to maintain noise margins.
RESET must be supported with LVCMOS levels as V
REF
may not
be stable during power-up. RESET is asynchronous and is intended
for power-up only and when low assures that all of the registers reset
to the Low State, Q outputs are low, and all input receivers, data and
clock, are switched off.
Product Pin Configuration
Q1
Q2
GND
VDDQ
Q3
Q4
Q5
GND
VDDQ
Q6
Q7
VDDQ
GND
Q8
Q9
VDDQ
GND
Q10
Q11
Q12
VDDQ
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
D1
D2
GND
VDD
D3
D4
D5
D6
D7
CLK
CLK
VDD
GND
VREF
RESET
D8
D9
D10
D11
D12
VDD
Pericom’s PI74SSTV16857 is characterized for operation from
0° to 70°C.
Product Pin Description
Pin Name
RESET
CLK
CLK
D
Q
GND
V
DD
V
DDQ
V
REF
Description
Reset (Active Low)
Clock Input
Clock Input
Data Input
Data Output
Ground
Core Supply Voltage
Output Supply Voltage
Input Reference Voltage
Logic Block Diagram
CLK
CLK
RESET
38
39
34
R
CLK
D
1
Q1
PS8460H
11/10/08
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74SSTV16857
14-Bit Registered Buffer
Truth Table
(1)
Inputs
RESET
L
H
Η
H
CLK
X
↑
↑
L or H
CLK
X
↓
↓
L or H
D
X
H
L
X
Outputs
Q
L
H
L
Q o
(2 )
Notes:
1. H = High Signal Level
2. Output level before the
L = Low Signal Level
indicated steady state
↑
= Transition LOW-to-HIGH
input conditions were
↓
= Transition HIGH-to-LOW
established.
X = Irrelevant
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Ite m
Storage temperature
Supply voltage
Input voltage
(1)
Output voltage
(1,2)
Input clamp current
Output clamp current
Continuous output current
V
DD
, V
DDQ
or GND current/pin
Package Thermal Impedance
(3)
Symbol/Conditions
T
stg
V
DD
or V
DDQ
V
I
V
O
I
IK
, V
I
<0
I
OK
, V
O
<0
I
O
, V
O
= 0 to V
DDQ
I
DD
, I
DDQ
or I
GND
θJ
A
Ratings
–65 to 150
–0.5 to 3.6
–0.5 to V
DD
+0.5
–0.5 to V
DDQ
+0.5
–50
± 50
± 50
±100
70
Units
°C
V
mA
°C/W
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Notes:
1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed.
2. This current will flow only when the output is in the high state level V
O
> V
DDQ
.
3. The package thermal impedance is calculated in accordance with JESD 51.
08-0291
2
PS8460H
11/10/08
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74SSTV16857
14-Bit Registered Buffer
Recommended Operating Conditions
Parame te rs
V
DD
V
DDQ
V
REF
V
TT
V
IH
V
IL
V
IH
V
IL
V
IN
V
ID
V
IX
I
O H
I
O L
T
A
Supply Voltage
I/O Supply Voltage
Reference Voltage V
REF
= 0.5X V
DDQ
Termination Voltage
DC Input High Voltage
DC Input Low Voltage
Input High Voltage
Input Low Voltage
Input Voltage Level
Input Differential Voltage
RESET
Data Inputs
De s cription
M in.
2. 3
2. 3
1.15
V
REF
–0.04
V
REF
+0.15
–0 . 3
1. 7
–0.3
–0.3
0.36
(V
DDQ
/2) –0.2
V
DDQ
+0.6
(V
DDQ
/2) +0.2
–20
20
0
70
ºC
mA
Nom.
2. 5
2.5
1.25
V
REF
M ax.
2.7
2.7
1.35
V
REF
+0.04
V
DDQ
+0.3
V
REF
–0.15
V
DDQ
+0.3
0.8
V
Units
CLK,CLK
Cross Point Voltage of Differential Clock Pair
High- Level Output Current
Low- Level Output Current
Operating Free- Air Temperature
08-0291
3
PS8460H
11/10/08
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74SSTV16857
14-Bit Registered Buffer
DC Electrical Characteristics
(Over the Operating Range, T
A
= 0°C to +70°C, V
DD
= 2.5V ±200mV, V
DDQ
= 2.5V ±200mV)
Pa ra me te rs
V
IK
V
O H
Te s t Co nditio ns
I
I
=–18 mA
I
OH
= –10 0
μ
A
I
OH
=–16 mA
I
OL
= 10 0
μ
A
I
OH
=16 mA
V
I
= V
D
o r GN D
D
RES ET = GN D
V
I
= V
IH
(AC ) o r V
I
(AC ),
RES ET = V
D
D
RES ET = V
D
D
V
I
= V
IH (A )
o r V
IL(A )
,
C
C
C K and C K switching
5 0 % d uty cycle
RES ET = V
D
D
V
I
= V
IH (A )
o r V
IL(A )
,
C
C
C K and C K switching
5 0 % d uty cycle. O ne d ata
inp ut switching at half clo ck
freq uency, 5 0 % d uty cycle
I
OH
= – 2 0 mA
I
OL
= 2 0 mA
I
O
= 2 0 mA, T
A
= 2 5 °C
V
I
= V
R F
± 3 5 0 mV
E
=
V
ICR
1. 2 5 V, V
I(PP)
= 3 6 0 mV
2 . 3 V- 2 . 7 V
2 . 3 V- 2 . 7 V
2.5V
2.5V
7
7
V
CC
2.3V
2 . 3 V- 2 . 7 V
2.3V
2 . 3 V- 2 . 7 V
2.3V
2.7V
V
D
–0 . 2 V
D
1.95
0.2
0.35
5
10
56
μ
A
V
M in.
Typ.
(1)
M ax.
–1.2
Units
V
O L
I
I
All Inp uts,
S tand b y (S tatic)
I
D
D
O p erating S tatic
Dynamic
O p erating - C lo ck
o nly
I
D D
D
Dynamic
O p erating - p er
each d ata inp ut
mA
μ
A/
clo ck
MHz
52
I
O
= 0
2.7V
9
μ
A/
clo ck
MHz
Data
20
20
6
o hm
r
OH
r
OL
r
O
(
Δ
)
C
I
O utp ut High
O utp ut Lo w
r
OH-
r
OL
Data inp uts
C K and C K
2.0
2.0
3.5
3.5
pF
Notes:
4. Typical values are at V
DD
= Nominal V
DD
, T
A
= +25°C.
08-0291
4
PS8460H
11/10/08
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74SSTV16857
14-Bit Registered Buffer
Timing Requirements
(over recommended operating free-air temperature range
,
unless otherwise noted)
V
DD
=2
.
5V ± 0.2V
Unit
M in.
fclock
t
W
t
a c t
t
inact
t
S U
C lock F requency
P ulse Duration
Differential inputs active time
(5 )
M ax.
200
MHz
2.5
22
22
0.75
0.9
0.75
0.9
ns
↑
↑
O utput slew rate differential inputs inactive time
(6)
S etup time, fast slew rate
(7, 9)
S etup time, slow slew rate
(8, 9)
Hold time , fast slew rate
(7, 9)
Hold time, slow slew rate
(8 9)
,
Data before C K
↑
, C K
t
h
Data before C K , C K
↑
Notes:
5. Data inputs must be held low for a minimum time of t
act
min , after RESET is taken high
6. Data and clock inputs must be held at valid levels (not floating) for a minimum time of t
inact
min, after RESET is taken low.
7. Data signal input slew rate
≥
1 V/ns
8. Data signal input slew rate
≥
0.5V/ns and <1V/ns
9. CLK, CLK input slew rates are
≥
1 V/ns.
Switching characteristics
(over recommended operating free-air temperature range, unless otherwise noted.)
(See test circuits and switching waveforms).
Parame te r
f
mx
a
t
pd
t
ph
l
From
(Input)
To
(Output)
V
D
= 2.5V ±0.2V
D
M in.
200
Typ.
M ax.
Units
MHz
2 .8
5.0
ns
CLK, CLK
RESET
Q
Q
1.1
08-0291
5
PS8460H
11/10/08
京公网安备 11010802033920号
EEWORLD
