MX30LF1208AA
MX30LF1208AA
512M-bit NAND Flash Memory
P/N: PM1713
1
REV. 1.3, DEC. 19, 2013
MX30LF1208AA
Contents
1. FEATURES........................................................................................................................................4
2. GENERAL DESCRIPTIONS .............................................................................................................4
Figure 1. MX30LF1208AA Logic Diagram.............................................................................................. 4
2-1.
3-1.
ORDERING INFORMATION ...................................................................................................5
PIN DESCRIPTIONS...............................................................................................................7
3. PIN CONFIGURATIONS ...................................................................................................................6
4. PIN FUNCTIONS ...............................................................................................................................8
5. BLOCK DIAGRAM ............................................................................................................................9
Figure 2. AC Waveform for Command / Address/Data Latch Timing ................................................... 10
Figure 3. AC Waveforms for Address Input Cycle ................................................................................ 10
6. DEVICE OPERATIONS ...................................................................................................................10
Figure 4. AC Waveforms for Command Input Cycle ............................................................................ 11
Figure 5. AC Waveforms for Data Input Cycle ..................................................................................... 11
Figure 6. AC Waveforms for Read Cycle ............................................................................................. 12
Figure 7. AC Waveforms for Read Operation (Intercepted by CE#) .................................................... 13
Figure 8. Read Operation with CE# Don't Care ................................................................................... 14
Figure 9. AC Waveforms for Sequential Data Out Cycle (After Read) ................................................. 14
Figure 10. AC Waveforms for Random Data Output ............................................................................ 15
Figure 11. AC Waveforms for Cache Read .......................................................................................... 17
Figure 12. AC Waveforms for Program Operation after Command 80H .............................................. 18
Figure 13. AC Waveforms for Random Data In
(For Page program) .................................... 19
Figure 14. Program Operation with CE# Don't Care ............................................................................ 20
Figure 15-1. AC Waveforms for Cache Program ................................................................................. 22
Figure 15-2. Sequence of Cache Program ......................................................................................... 23
Figure 16. AC Waveforms for Erase Operation .................................................................................... 24
Figure 17. AC Waveforms for ID Read Operation ................................................................................ 25
Figure 18. AC Waveforms for Status Read Operation ......................................................................... 26
Figure 19. Reset Operation .................................................................................................................. 27
7. PARAMETERS ................................................................................................................................28
7-1.
Figure 20. Device Under Test ............................................................................................................... 30
Table 1. Operating Range .................................................................................................................... 29
Table 2. DC Characteristics.................................................................................................................. 29
Table 3. Capacitance............................................................................................................................ 29
ABSOLUTE MAXIMUM RATINGS .......................................................................................28
P/N: PM1713
2
REV. 1.3, DEC. 19, 2013
MX30LF1208AA
Table 4. AC Testing Conditions ............................................................................................................ 30
Table 5. Program, Read and Erase Characteristics ............................................................................. 30
Table 6. AC Characteristics over Operating Range.............................................................................. 31
8. SCHEMATIC CELL LAYOUT AND ADDRESS ASSIGNMENT ......................................................32
Table 7. Address Allocation .................................................................................................................. 32
9. OPERATION MODES: LOGIC AND COMMAND TABLES ............................................................33
Figure 21. Bit Assignment (HEX Data) ................................................................................................. 34
Table 8. Logic Table ............................................................................................................................. 33
Table 9. HEX Command Table ............................................................................................................. 34
Table 10. Status Output........................................................................................................................ 35
Table 11. ID Codes Read Out by ID Read Command 90H .................................................................. 35
Table 12. The Definition of 3rd Code of ID Table
................................................................................ 36
Table 13. The Definition of 4th Code of ID Table
................................................................................. 36
9-1.
9-2.
Figure 22. R/B# Pin Timing Information ............................................................................................... 37
Figure 23. Power On/Off Sequence ..................................................................................................... 38
Figure 24. Enable Programming .......................................................................................................... 39
Figure 25. Disable Programming ......................................................................................................... 39
Figure 26. Enable Erasing.................................................................................................................... 39
Figure 27. Disable Erasing ................................................................................................................... 39
R/B#: TERMINATION FOR THE READY/BUSY# PIN (R/B#) .............................................37
POWER ON/OFF SEQUENCE .............................................................................................38
10. SOFTWARE ALGORITHM..............................................................................................................40
10-1. INVALID BLOCKS (BAD BLOCKS) .....................................................................................40
Figure 28. Bad Blocks .......................................................................................................................... 40
Table 14. Valid Blocks .......................................................................................................................... 40
Figure 29. Bad Block Test Flow ............................................................................................................ 41
Table 15. Failure Modes ....................................................................................................................... 41
Figure 30. Failure Modes ..................................................................................................................... 42
Figure 31. Program Flow Chart ............................................................................................................ 42
Figure 32. Erase Flow Chart ................................................................................................................ 43
Figure 33. Read Flow Chart ................................................................................................................. 43
10-2. BAD BLOCK TEST FLOW ...................................................................................................41
10-3. FAILURE PHENOMENA FOR READ/PROGRAM/ERASE OPERATIONS .........................41
10-4. PROGRAM ............................................................................................................................42
10-5. ERASE ..................................................................................................................................42
11. PACKAGE INFORMATION .............................................................................................................45
12. REVISION HISTORY ......................................................................................................................47
P/N: PM1713
3
REV. 1.3, DEC. 19, 2013
MX30LF1208AA
512Mbit (64M x 8 bit) NAND Flash Memory
1. FEATURES
• 512Mbit SLC NAND Flash
- 64M x 8 bit
- 32 K pages of (2,048+64) bytes each
- 512 blocks of 64 pages each
• Multiplexed Command/Address/Data
• 2 MByte User Redundancy
- 64 bytes attached to each page
• Fast Read Access
- First-byte latency: 25us
- Sequential read: 30ns/byte
• Cache Read Support
• Page Program Operation
• Cache Program
-
Internal cache of (2,048+64) bytes
• Program Time:
Page program 250us (typ.)
• Single Voltage Operation:
3.3V
• Low Power Dissipation
- Max. 30mA active
current (RD/PGM/ERS)
• Automatic Sleep Mode
- 50uA (Max) standby current
• Block Erase Architecture
- Block size: (128K+4K) bytes per block
- 512 blocks, 64 pages each
- Block Erase Time: 2ms (Typ.)
•
Hardware Data Protection:
WP# pin
•
Multiple Device Status Indicators
- Ready/Busy (R/B#) pin
- Status Register
•
Chip Enable Don't Care
- Simplify System Interface
•
Status Register
• Electronic Signature (Four Cycles)
• High Reliability
- Endurance: 100K cycles
(with 1-bit ECC per 528-byte)
- Data Retention: 10 years
• Wide Temperature Operating Range:
-40°C to +85°C
•
Package:
- 48-TSOP(I) (12mm x 20mm)
- 63-ball 9mmx11mm VFBGA
- All packaged devices are RoHS Compliant &
Halogen-free
Fast programming is supported, enabling page
programming at a rate of 8MB/sec (approx.)
The MX30LF1208AA power consumption is
30 mA during all modes of operations (Read/
Program/Erase), and 50uA in standby mode.
2. GENERAL DESCRIPTIONS
The MX30LF1208AA is a 512Mb SLC NAND Flash
memory device. Its standard NAND Flash features
and reliable quality make it most suitable for
embedded system code and data storage usage.
The MX30LF1208AA is typically accessed in pages
of 2,112 bytes, both for read and for program
operations.
The MX30LF1208AA array is organized as
512 blocks, which is composed by 64 pages of
(2,048+64)-byte in two NAND strings structure with
32 serial connected cells in each string. Each page
has an additional 64 bytes for ECC and other pur-
poses. The device has an on-chip buffer of 2,112
bytes for data load and access.
The Cache Read Operation of the
MX30LF1208AA enable first-byte read-access la-
tency of 25us and sequential read of 30ns per byte.
P/N: PM1713
4
Figure 1. MX30LF1208AA Logic Diagram
ALE
CLE
CE#
RE#
WE#
WP#
IO7-
IO IO0
MLC1Gb
512Mb
R/B#
REV. 1.3, DEC. 19, 2013
MX30LF1208AA
2-1. ORDERING INFORMATION
Part Name Description
MX 30 L F 12 08 A A - T
I
x
RESERVE
OPERATING TEMPERATURE:
I: Industrial (-40°C to 85°C)
PACKAGE TYPE:
T: 48TSOP
XK: 0.8mm Ball Pitch, 0.45mm Ball Size and 1.0mm height of VFBGA
Package: Package: RoHS Compliant & Halogen-free
GENERATION: (Tech. Code)
A
MODE:
A = Die#: 1, CE#: 1, R/B#: 1, Reserve: 0
OPTION CODE:
08 = x8
DENSITY:
12 = 512Mbit
CLASSIFICATION:
F = SLC + Large Block
VOLTAGE:
L = 2.7V to 3.6V
TYPE:
30 = NAND Flash
BRAND:
MX
PART NUMBER
MX30LF1208AA-TI
MX30LF1208AA-XKI
ORGANIZATION
x8
x8
VCC RANGE
2.7V - 3.6 Volt
2.7V - 3.6 Volt
PACKAGE
48-TSOP
63-VFBGA
TEMPERATUR GRADE
Industrial (-40 to 85°C)
Industrial (-40 to 85°C)
P/N: PM1713
5
REV. 1.3, DEC. 19, 2013
京公网安备 11010802033920号
EEWORLD
