EFR32xG14 Wireless Gecko
Reference Manual
The Wireless Gecko portfolio of SoCs (EFR32) includes Mighty
Gecko (EFR32MG14), Blue Gecko (EFR32BG14), and Flex
Gecko (EFR32FG14) families. With support for Zigbee
®
, Thread,
Bluetooth Low Energy (BLE) and proprietary protocols, the Wire-
less Gecko portfolio is ideal for enabling energy-friendly wireless
networking for IoT devices.
The single-die solution provides industry-leading energy efficiency, ultra-fast wakeup
times, a scalable high-power amplifier, an integrated balun and no-compromise MCU
features.
KEY FEATURES
• 32-bit ARM® Cortex-M4 core with 40 MHz
maximum operating frequency
• Scalable Memory and Radio configuration
options available in several footprint
compatible QFN packages
• 12-channel Peripheral Reflex System
enabling autonomous interaction of MCU
peripherals
• Autonomous Hardware Crypto Accelerator
and True Random Number Generator
• Integrated balun for 2.4 GHz and
integrated PA with up to 19 dBm transmit
power for 2.4 GHz and 20 dBm transmit
power for Sub-GHz radios
• Integrated DC-DC with RF noise mitigation
Core / Memory
Clock Management
H-F Crystal
Oscillator
Auxiliary H-F RC
Oscillator
L-F Crystal
Oscillator
H-F
RC Oscillator
L-F
RC Oscillator
Ultra L-F RC
Oscillator
Energy Management
Voltage
Regulator
DC-DC
Converter
Brown-Out
Detector
Voltage Monitor
Other
CRYPTO
CRC
ARM Cortex M4 processor
with DSP extensions, FPU and MPU
TM
Flash Program
Memory
Power-On Reset
True Random
Number Generator
SMU
Debug Interface
RAM Memory
LDMA Controller
32-bit bus
Peripheral Reflex System
Radio Transceiver
RFSENSE
Sub GHz
I
LNA
RF Frontend
PA
Q
DEMOD
BUFC
FRC
Serial
Interfaces
USART
I/O Ports
External
Interrupts
General
Purpose I/O
Timers and Triggers
Timer/Counter
Protocol Timer
Analog I/F
ADC
Analog
Comparator
IDAC
PGA
To Sub GHz
receive I/Q
mixers and PA
IFADC
Low Energy
UART
TM
Low Energy
Timer
Low Energy
Sensor Interface
CRC
RAC
RFSENSE
AGC
I
2
C
Pin Reset
Pulse Counter
Real Time
Counter and
Calendar
Watchdog Timer
2.4 GHz
BALUN
I
LNA
RF Frontend
PA
Q
Frequency
Synthesizer
To 2.4 GHz receive
I/Q mixers and PA
MOD
Pin Wakeup
To Sub GHz
and 2.4 GHz PA
VDAC
Cryotimer
Op-Amp
Lowest power mode with peripheral operational:
EM0—Active
EM1—Sleep
EM2—Deep Sleep
EM3—Stop
EM4—Hibernate
EM4—Shutoff
silabs.com
| Building a more connected world.
Rev. 1.1
Table of Contents
1. About This Document . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Introduction.
1.2 Conventions
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
26
.26
.26
.27
1.3 Related Documentation
2. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Introduction.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
2.2 Block Diagrams .
28
.28
.29
.30
.32
.32
.32
.33
.33
.33
.33
.33
.34
.34
.34
.35
.36
.36
2.3 MCU Features Overview .
2.4 Oscillators and Clocks .
2.6 Modulation Modes .
2.7 Transmit Mode
2.8 Receive Mode .
2.9 Data Buffering .
.
.
.
.
.
.
.
.
.
.
2.5 RF Frequency Synthesizer
2.10 Unbuffered Data Transfer
2.11 Frame Format Support
2.12 Hardware CRC Support .
2.13 Convolutional Encoding / Decoding .
2.14 Binary Block Encoding / Decoding
2.16 Timers .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
2.15 Data Encryption and Authentication .
2.17 RF Test Modes .
3. System Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Introduction.
3.2 Features.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
37
.37
.38
.38
.39
.40
3.3 Functional Description . . . . .
3.3.1 Interrupt Operation . . . .
3.3.2 Interrupt Request Lines (IRQ)
4. Memory and Bus System . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Introduction.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
4.2 Functional Description . . . . . . . .
4.2.1 Peripheral Non-Word Access Behavior
4.2.2 Bit-banding . . . . . . . . . .
4.2.3 Peripheral Bit Set and Clear . . . .
4.2.4 Peripherals . . . . . . . . . .
4.2.5 Bus Matrix . . . . . . . . . .
41
.42
.43
.45
.45
.46
.47
.48
.51
4.3 Access to Low Energy Peripherals (Asynchronous Registers) .
silabs.com
| Building a more connected world.
Rev. 1.1 | 2
4.3.1 Writing . . . .
4.3.2 Reading . . . .
4.3.3 FREEZE Register
4.4 Flash .
4.5 SRAM
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.52
.54
.54
.54
.55
.56
.58
.58
.59
.60
.60
.60
.61
.62
.62
.62
.63
.65
.65
.66
.67
.68
.68
.69
.70
.71
.72
.73
.74
.75
.76
.77
.78
.79
.80
.81
.82
.83
.84
.85
.86
.87
.88
.89
.89
.90
.91
4.6 DI Page Entry Map .
4.7 DI Page Entry Description . . . . . . . . . . . . . . . . .
4.7.1 CAL - CRC of DI-page and calibration temperature . . . . . .
4.7.2 EXTINFO - External Component description . . . . . . . .
4.7.3 EUI48L - EUI48 OUI and Unique identifier . . . . . . . . .
4.7.4 EUI48H - OUI . . . . . . . . . . . . . . . . . .
4.7.5 CUSTOMINFO - Custom information
. . . . . . . . . .
4.7.6 MEMINFO - Flash page size and misc. chip information . . . .
4.7.7 UNIQUEL - Low 32 bits of device unique number . . . . . .
4.7.8 UNIQUEH - High 32 bits of device unique number . . . . . .
4.7.9 MSIZE - Flash and SRAM Memory size in kB . . . . . . . .
4.7.10 PART - Part description . . . . . . . . . . . . . . .
4.7.11 DEVINFOREV - Device information page revision . . . . . .
4.7.12 EMUTEMP - EMU Temperature Calibration Information . . . .
4.7.13 ADC0CAL0 - ADC0 calibration register 0 . . . . . . . . .
4.7.14 ADC0CAL1 - ADC0 calibration register 1 . . . . . . . . .
4.7.15 ADC0CAL2 - ADC0 calibration register 2 . . . . . . . . .
4.7.16 ADC0CAL3 - ADC0 calibration register 3 . . . . . . . . .
4.7.17 HFRCOCAL0 - HFRCO Calibration Register (4 MHz) . . . . .
4.7.18 HFRCOCAL3 - HFRCO Calibration Register (7 MHz) . . . . .
4.7.19 HFRCOCAL6 - HFRCO Calibration Register (13 MHz) . . . .
4.7.20 HFRCOCAL7 - HFRCO Calibration Register (16 MHz) . . . .
4.7.21 HFRCOCAL8 - HFRCO Calibration Register (19 MHz) . . . .
4.7.22 HFRCOCAL10 - HFRCO Calibration Register (26 MHz) . . . .
4.7.23 HFRCOCAL11 - HFRCO Calibration Register (32 MHz) . . . .
4.7.24 HFRCOCAL12 - HFRCO Calibration Register (38 MHz) . . . .
4.7.25 AUXHFRCOCAL0 - AUXHFRCO Calibration Register (4 MHz) .
4.7.26 AUXHFRCOCAL3 - AUXHFRCO Calibration Register (7 MHz) .
4.7.27 AUXHFRCOCAL6 - AUXHFRCO Calibration Register (13 MHz) .
4.7.28 AUXHFRCOCAL7 - AUXHFRCO Calibration Register (16 MHz) .
4.7.29 AUXHFRCOCAL8 - AUXHFRCO Calibration Register (19 MHz) .
4.7.30 AUXHFRCOCAL10 - AUXHFRCO Calibration Register (26 MHz)
4.7.31 AUXHFRCOCAL11 - AUXHFRCO Calibration Register (32 MHz) .
4.7.32 AUXHFRCOCAL12 - AUXHFRCO Calibration Register (38 MHz)
4.7.33 VMONCAL0 - VMON Calibration Register 0 . . . . . . . .
4.7.34 VMONCAL1 - VMON Calibration Register 1 . . . . . . . .
4.7.35 VMONCAL2 - VMON Calibration Register 2 . . . . . . . .
4.7.36 IDAC0CAL0 - IDAC0 Calibration Register 0 . . . . . . . .
4.7.37 IDAC0CAL1 - IDAC0 Calibration Register 1 . . . . . . . .
4.7.38 DCDCLNVCTRL0 - DCDC Low-noise VREF Trim Register 0 . .
4.7.39 DCDCLPVCTRL0 - DCDC Low-power VREF Trim Register 0 . .
4.7.40 DCDCLPVCTRL1 - DCDC Low-power VREF Trim Register 1 . .
silabs.com
| Building a more connected world.
Rev. 1.1 | 3
4.7.41
4.7.42
4.7.43
4.7.44
4.7.45
4.7.46
4.7.47
4.7.48
4.7.49
4.7.50
4.7.51
4.7.52
4.7.53
4.7.54
4.7.55
4.7.56
4.7.57
4.7.58
4.7.59
4.7.60
4.7.61
4.7.62
4.7.63
DCDCLPVCTRL2 - DCDC Low-power VREF Trim Register 2 . . . . . .
DCDCLPVCTRL3 - DCDC Low-power VREF Trim Register 3 . . . . . .
DCDCLPCMPHYSSEL0 - DCDC LPCMPHYSSEL Trim Register 0 . . . .
DCDCLPCMPHYSSEL1 - DCDC LPCMPHYSSEL Trim Register 1 . . . .
VDAC0MAINCAL - VDAC0 Cals for Main Path . . . . . . . . . . .
VDAC0ALTCAL - VDAC0 Cals for Alternate Path . . . . . . . . . .
VDAC0CH1CAL - VDAC0 CH1 Error Cal . . . . . . . . . . . . .
OPA0CAL0 - OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=1
OPA0CAL1 - OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=1
OPA0CAL2 - OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=1
OPA0CAL3 - OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=1
OPA1CAL0 - OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=1
OPA1CAL1 - OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=1
OPA1CAL2 - OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=1
OPA1CAL3 - OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=1
OPA0CAL4 - OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=0
OPA0CAL5 - OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=0
OPA0CAL6 - OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=0
OPA0CAL7 - OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=0
OPA1CAL4 - OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=0
OPA1CAL5 - OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=0
OPA1CAL6 - OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=0
OPA1CAL7 - OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.92
.93
.93
.94
.95
.96
.97
.98
.99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
5. Radio Transceiver
5.1 Introduction.
.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 115
6. DBG - Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.1 Introduction.
6.2 Features.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 116
. 116
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
116
117
117
117
118
118
119
119
120
120
120
121
121
122
122
123
123
6.3 Functional Description . . . . . . . . .
6.3.1 Debug Pins. . . . . . . . . . .
6.3.2 Debug and EM2 Deep Sleep/EM3 Stop .
6.3.3 Authentication Access Point . . . . .
6.3.4 Debug Lock . . . . . . . . . .
6.3.5 AAP Lock . . . . . . . . . . .
6.3.6 Debugger Reads of Actionable Registers
6.3.7 Debug Recovery . . . . . . . . .
6.4 Register Map .
.
.
.
.
.
.
.
.
.
.
.
. 119
6.5 Register Description . . . . . . . . . . .
6.5.1 AAP_CMD - Command Register . . . .
6.5.2 AAP_CMDKEY - Command Key Register .
6.5.3 AAP_STATUS - Status Register . . . .
6.5.4 AAP_CTRL - Control Register . . . . .
6.5.5 AAP_CRCCMD - CRC Command Register
6.5.6 AAP_CRCSTATUS - CRC Status Register .
6.5.7 AAP_CRCADDR - CRC Address Register .
6.5.8 AAP_CRCRESULT - CRC Result Register .
silabs.com
| Building a more connected world.
Rev. 1.1 | 4
6.5.9 AAP_IDR - AAP Identification Register .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 124
7. MSC - Memory System Controller
7.1 Introduction.
7.2 Features.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . . . . . . . . . . . . . . . . . . . . 125
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 125
. 126
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
127
127
128
128
129
129
129
130
130
131
131
132
133
133
135
135
136
137
138
139
139
140
141
142
143
144
145
146
146
147
148
149
150
150
151
152
7.3 Functional Description . . . . . . . . . . . . . .
7.3.1 User Data (UD) Page Description . . . . . . . .
7.3.2 Lock Bits (LB) Page Description . . . . . . . . .
7.3.3 Device Information (DI) Page . . . . . . . . .
7.3.4 Bootloader . . . . . . . . . . . . . . . .
7.3.5 Device Revision . . . . . . . . . . . . . .
7.3.6 Post-reset Behavior . . . . . . . . . . . . .
7.3.7 Flash Startup . . . . . . . . . . . . . . .
7.3.8 Wait-states . . . . . . . . . . . . . . . .
7.3.9 Suppressed Conditional Branch Target Prefetch (SCBTP)
7.3.10 Cortex-M4 If-Then Block Folding . . . . . . . .
7.3.11 Instruction Cache . . . . . . . . . . . . .
7.3.12 Low Voltage Flash Read . . . . . . . . . . .
7.3.13 Erase and Write Operations. . . . . . . . . .
7.4 Register Map .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 134
7.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.1 MSC_CTRL - Memory System Control Register . . . . . . . . . . . . . .
7.5.2 MSC_READCTRL - Read Control Register . . . . . . . . . . . . . . .
7.5.3 MSC_WRITECTRL - Write Control Register . . . . . . . . . . . . . . .
7.5.4 MSC_WRITECMD - Write Command Register . . . . . . . . . . . . . .
7.5.5 MSC_ADDRB - Page Erase/Write Address Buffer . . . . . . . . . . . . .
7.5.6 MSC_WDATA - Write Data Register . . . . . . . . . . . . . . . . . .
7.5.7 MSC_STATUS - Status Register . . . . . . . . . . . . . . . . . . .
7.5.8 MSC_IF - Interrupt Flag Register . . . . . . . . . . . . . . . . . . .
7.5.9 MSC_IFS - Interrupt Flag Set Register . . . . . . . . . . . . . . . . .
7.5.10 MSC_IFC - Interrupt Flag Clear Register . . . . . . . . . . . . . . . .
7.5.11 MSC_IEN - Interrupt Enable Register . . . . . . . . . . . . . . . . .
7.5.12 MSC_LOCK - Configuration Lock Register . . . . . . . . . . . . . . .
7.5.13 MSC_CACHECMD - Flash Cache Command Register . . . . . . . . . . .
7.5.14 MSC_CACHEHITS - Cache Hits Performance Counter . . . . . . . . . . .
7.5.15 MSC_CACHEMISSES - Cache Misses Performance Counter . . . . . . . . .
7.5.16 MSC_MASSLOCK - Mass Erase Lock Register
. . . . . . . . . . . . .
7.5.17 MSC_STARTUP - Startup Control . . . . . . . . . . . . . . . . . .
7.5.18 MSC_CMD - Command Register . . . . . . . . . . . . . . . . . .
7.5.19 MSC_BOOTLOADERCTRL - Bootloader Read and Write Enable, Write Once Register
7.5.20 MSC_AAPUNLOCKCMD - Software Unlock AAP Command Register . . . . . .
7.5.21 MSC_CACHECONFIG0 - Cache Configuration Register 0 . . . . . . . . . .
8. LDMA - Linked DMA Controller. . . . . . . . . . . . . . . . . . . . . . . . 153
8.1 Introduction. .
8.1.1 Features
8.2 Block Diagram.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 153
. 154
. 155
silabs.com
| Building a more connected world.
Rev. 1.1 | 5
京公网安备 11010802033920号
EEWORLD
