EEWORLDEEWORLDEEWORLD

Part Number

Search

534FC000358DGR

Description
QUAD FREQUENCY XO, OE PIN 2
CategoryPassive components   
File Size445KB,12 Pages
ManufacturerSilicon Laboratories Inc
Download Datasheet Parametric View All

534FC000358DGR Online Shopping

Suppliers Part Number Price MOQ In stock  
534FC000358DGR - - View Buy Now

534FC000358DGR Overview

QUAD FREQUENCY XO, OE PIN 2

534FC000358DGR Parametric

Parameter NameAttribute value
typeXO (Standard)
Frequency - Output 110MHz
Frequency - Output 225MHz
Frequency - Output 330.72MHz
Frequency - Output 438.4MHz
Functionenable/disable
outputLVDS
Voltage - Power2.5V
frequency stability±7ppm
Operating temperature-40°C ~ 85°C
Current - Power (maximum)98mA
size/dimensions0.276" long x 0.197" wide (7.00mm x 5.00mm)
high0.071"(1.80mm)
Package/casing8-SMD, no leads
Current - Power (disabled) (maximum)75mA
Si534
R
EVISION
D
Q
UAD
F
R E Q U E N C Y
C
RYSTAL
O
S C I L L A T O R
(XO)
(10 M H
Z TO
1 . 4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
Four selectable output frequencies
®
3rd generation DSPLL with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
FS[1]
7
NC
OE
GND
1
2
3
8
FS[0]
6
5
4
V
DD
Description
The Si534 quad frequency XO utilizes Silicon Laboratories’ advanced
DSPLL
®
circuitry to provide a low jitter clock at high frequencies. The Si534
is available with any-rate output frequency from 10 to 945 MHz and select
frequencies to 1400 MHz. Unlike a traditional XO where a different crystal is
required for each output frequency, the Si534 uses one fixed crystal to
provide a wide range of output frequencies. This IC-based approach allows
the crystal resonator to provide exceptional frequency stability and reliability.
In addition, DSPLL clock synthesis provides superior supply noise rejection,
simplifying the task of generating low jitter clocks in noisy environments
typically found in communication systems. The Si534 IC-based XO is factory
configurable for a wide variety of user specifications including frequency,
supply voltage, output format, and temperature stability. Specific
configurations are factory programmed at time of shipment, thereby
eliminating long lead times associated with custom oscillators.
CLK–
CLK+
(LVDS/LVPECL/CML)
FS[1]
7
NC
OE
GND
1
2
3
8
FS[0]
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
FS[1]
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
FS[0]
(CMOS)
OE
GND
Rev. 1.4 6/18
Copyright © 2018 by Silicon Laboratories
Si534
[Recommendation] Improvement of switching power supply protection circuit based on UC3842 (2)
2 Defects of UC3842 protection circuit   2.1 Defects of overload protection   When the power supply is overloaded or the output is short-circuited, the protection circuit of UC3842 is activated, reduc...
pushu009azx Analogue and Mixed Signal
【helper2416】The first batch of helper2416 uCOS II porting programs written by myself
[align=left][font=宋体][color=#ff0000]I posted to the wrong forum at first. I will post it back. . . [/color][/font][/align][align=left][font=宋体][size=10.5pt][color=#ff00ff]#include "all.h" OS_STK InitT...
陌路绝途 Embedded System
[Nucleo experience]——Some sharing of STM32L053 manual
[i=s] This post was last edited by qq849682862 on 2014-11-4 08:24 [/i] Share some of the STM32L053 manuals I just downloaded...
qq849682862 stm32/stm8
How to compile and use FAAD on WM
I used the cygwin-cegcc-mingw32ce-0.51.0-1 compiler to compile FFMPEG. After installing FAAD, I copied the FAAD.A and other files to the libavcodec directory of FFMPEG, but the compilation still faile...
samhesam Embedded System
Cross-clock domain: How to read low-frequency clock data instantly with high-frequency clock
Initiate a read command in the high-frequency clock domain to read data in the low-frequency clock domain. Since the read signal is in the high-frequency clock domain, the hold time is not enough to s...
stepan FPGA/CPLD
Google Glass for Modern Warfare
[color=#595959][backcolor=rgb(255, 255, 255)][font=Arial, Helvetica, sans-serif][size=14px]Google Glass connects to the electronic eyepiece of a semi-automatic rifle via WiFi, allowing people to aim a...
qwqwqw2088 Talking

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2901  339  1254  1839  2656  59  7  26  38  54 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号