EEWORLDEEWORLDEEWORLD

Part Number

Search

552CF000321DGR

Description
VCXO; DIFF/SE; DUAL FREQ; 10-141
CategoryPassive components   
File Size477KB,15 Pages
ManufacturerSilicon Laboratories Inc
Download Datasheet Parametric View All

552CF000321DGR Online Shopping

Suppliers Part Number Price MOQ In stock  
552CF000321DGR - - View Buy Now

552CF000321DGR Overview

VCXO; DIFF/SE; DUAL FREQ; 10-141

552CF000321DGR Parametric

Parameter NameAttribute value
typeVCXO
Frequency - Output 184MHz, 102.4MHz
Frequency - Output 2-
Frequency - Output 3-
Frequency - Output 4-
Functionenable/disable
outputCMOS
Voltage - Power3.3V
frequency stability±50ppm
Operating temperature-40°C ~ 85°C
Current - Power (maximum)98mA
size/dimensions0.276" long x 0.197" wide (7.00mm x 5.00mm)
high0.071"(1.80mm)
Package/casing6-SMD, no leads
Current - Power (disabled) (maximum)75mA
Si 5 5 2
R
EVISION
D
D
U A L
F
REQUENCY
V
OLTAGE
- C
ON TROLLED
C
R Y S TA L
O
SCILLATOR
(VCXO) 10 MH
Z TO
1 . 4 G H
Z
Features
Available with any-rate output
frequencies from 10–945 MHz and
selected frequencies to 1.4 GHz
Two selectable output frequencies
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Applications
SONET/SDH
xDSL
10 GbE LAN/WAN
Ordering Information:
Low-jitter clock generation
Optical modules
Clock and data recovery
See page 10.
Description
The Si552 dual-frequency VCXO utilizes Silicon Laboratories’ advanced
DSPLL
®
circuitry to provide a very low jitter clock for all output frequencies.
The Si552 is available with any-rate output frequency from 10 to 945 MHz
and selected frequencies to 1400 MHz. Unlike traditional VCXOs, where a
different crystal is required for each output frequency, the Si552 uses one
fixed crystal frequency to provide a wide range of output frequencies. This
IC-based approach allows the crystal resonator to provide exceptional
frequency stability and reliability. In addition, DSPLL clock synthesis
provides superior supply noise rejection, simplifying the task of generating
low-jitter clocks in noisy environments typically found in communication
systems. The Si552 IC-based VCXO is factory-configurable for a wide
variety of user specifications including frequency, supply voltage, output
format, tuning slope, and temperature stability. Specific configurations are
factory programmed at time of shipment, thereby eliminating the long lead
times associated with custom oscillators.
Pin Assignments:
See page 9.
(Top View)
V
C
1
2
3
6
5
4
V
DD
FS
GND
CLK–
CLK+
Functional Block Diagram
V
DD
CLK- CLK+
Fixed
Frequency XO
Any-rate
10–1400 MHz
DSPLL
®
Clock Synthesis
ADC
V
C
FS
GND
Rev. 1.2 6/18
Copyright © 2018 by Silicon Laboratories
Si552
How to measure the resistance of water? Which one is greater, the resistance of the fat house happy water or this one?
How to measure the resistance of water? Which one is greater, the resistance of the fat house happy water or this one?...
aigtekatdz Test/Measurement
Design of high-precision semiconductor laser drive power supply and temperature control circuit
Design of high-precision semiconductor laser drive power supply and temperature control circuit: In order to solve the problem that the output power and wavelength of the semiconductor laser light sou...
amperhong Power technology
LM3S3739 JTAG port is locked, how to unlock it?
LM3S3739 JTAG port lock problem, tried all the methods found on the Internet but none of them worked, I only have JLINK V8, SEGGER is V4.15W. I changed a new film and can see the device, one is to unl...
yuchenglin Microcontroller MCU
【microbit crowdfunding】Project progress 2017-03-05
I have been busy lately and will be on a business trip next week, so the update is a bit slow. Microbit's current progress: [list=1] [*]PCB is being made[*]Components have been purchased[*]Should be r...
dcexpert MicroPython Open Source section
FPGA IO is abnormal after power-on
Today I found a magical phenomenon. When I powered on the CYCLONE IV I had programmed, all the IO outputs were around 1.5V, and the program obviously did not run. However, when I plugged in and unplug...
petty2012 FPGA/CPLD
I once saw an article saying that the core frequency of 1114 can be modified
I want to modify it myself so that 1114 can run at 72M, but I can't find the configuration register. Which hero can give me some advice?...
gl4365 NXP MCU

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 623  2773  1289  585  348  13  56  26  12  7 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号