INTEGRATED CIRCUITS
SC28L194
Quad UART for 3.3 V and 5 V supply
voltage
Product data sheet
Supersedes data of 2001 Feb 13
IC19 Data Handbook
2006 Aug 15
Philips
Semiconductors
Philips Semiconductors
Product data sheet
Quad UART for 3.3 V and 5 V supply voltage
SC28L194
DESCRIPTION
The Philips 28L194 Quad UART is a single chip CMOS-LSI
communications device that provides 4 full-duplex asynchronous
channels with significantly deeper 16 byte FIFOs, Automatic in-band
flow control using Xon/Xoff characters defined by the user and
address recognition in the Wake-up mode. Synchronous bus
interface is used for all communication between host and QUART. It
is fabricated in Philips state of the art CMOS technology that
combines the benefits of low cost, high density and low power
consumption.
The operating speed of each receiver and transmitter can be
selected independently from one of 22 fixed baud rates, a 16X clock
derived from one of two programmable baud rate counters or one of
three external 16X clocks (1 available at 1x clock rate). The baud
rate generator and counter can operate directly from a crystal or
from seven other external or internal clock inputs. The ability to
independently program the operating speed of the receiver and
transmitter makes the Quad UART particularly attractive for dual
speed full duplex channel applications such as clustered terminal
systems. The receivers and transmitters are buffered with FIFOs of
16 characters to minimize the potential for receiver overrun and to
reduce interrupt overhead. In addition, a handshaking capability and
in-band flow control are provided to disable a remote UART
transmitter when the receiver buffer is full or nearly so.
To minimize interrupt overhead an interrupt arbitration system is
included which reports the context of the interrupting UART via
direct access or through the modification of the interrupt vector. The
context of the interrupt is reported as channel number, type of
device interrupting (receiver COS etc.) and, for transmitters or
receivers, the fill level of the FIFO.
The Quad UART provides a power down mode in which the
oscillator is stopped but the register contents are maintained. This
results in reduced power consumption of several orders of
magnitudes. The Quad UART is fully TTL compatible when
operating from a single +5V or 3.3V power supply. Operation at 3.3V
or 5.0V is maintained with CMOS interface levels.
FEATURES
•
Single 3.3V and 5.0V power supply
•
Four Philips industry standard full duplex UART channels
•
Sixteen byte receiver FIFOs for each UART
•
Sixteen byte transmit FIFOs for each UART
•
In band flow control using programmable Xon/Xoff characters
•
Flow control using CTSN RTSN hardware handshaking
•
Automatic address detection in multi-drop mode
•
Three byte general purpose character recognition
•
Fast data bus, 15 ns data bus release time, 125 ns bus cycle time
•
Programmable interrupt priorities
•
Automatic identification of highest priority interrupt pending
•
Global interrupt and control registers ease setup and interrupt
•
Vectored interrupts with programmable interrupt vector formats
– Interrupt vector modified with channel number
– Interrupt vector modified with channel number and channel type
– Interrupt vector not modified
handling
•
IACKN and DACKN signal pins
•
Watch dog timer for each receiver (64 receive clock counts)
•
Programmable Data Formats:
– 5 to 8 data bits plus parity
– Odd, even force or no parity
– 1, 1.5 or 2 stop bits
•
Flexible baud rate selection for receivers and transmitters:
– 22 fixed rates; 50 - 230.4K baud or 100 to 460.8K baud
– Additional non-standard rates to 500K baud with internal
generators
– Two reload-counters provide additional programmable baud
rate generation
– External 1x or 16x clock inputs
– Simplified baud rate selection
Uses
•
Statistical Multiplexers
•
Data Concentrators
– Packet-switching networks
– Process Control
– Building or Plant Control
– Laboratory data gathering
– ISDN front ends
– Computer Networks
– Point-of-Sale terminals
•
1 MHz 1x and 16x data rates full duplex all channels.
•
Parity, framing and overrun error detection
•
False start bit detection
•
Line break detection and generation
•
Programmable channel mode
– Normal(full duplex)
– Diagnostic modes
automatic echo
local loop back
remote loop back
•
Automotive, cab and engine controls
•
Entertainment systems
– MIDDI keyboard control music systems
– Theater lighting control
•
Four I/O ports per UART for modem controls, clocks, RTSN, I/O,
etc.
– All I/O ports equipped with “Change of State Detectors”
•
Terminal Servers
– Computer-Printer/Plotter links
•
Two global inputs and two global outputs for general purpose I/O
•
Power down mode
•
On chip crystal oscillator, 2-8 MHz
•
TTL input levels. Outputs switch between full V
CC
and V
SS
•
High speed CMOS technology
•
80-pin Low Profile Quad Flat Pack LQFP and 68-pin PLCC
2
2006 Aug 15
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NOTE:
The Vss-ic and Vcc_i are for input and noise sensitive circuits. Sclk signals in the range of 3 to 6 ns and within TTL input levels may
alter expected read or write functions. The Vss _o and Vcc _o pins are used for the high current drivers. De-coupling capacitors should be used
as close to the device power pins as possible.
Address bit A6 is not used. See “Host Interface” section.
4 Vss_ic, 4 Vcc_i, 4 Vss_o, 2 Vcc_o, 2Vcc_c
2006 Aug 15
Pin Assignments
PINOUT - 68 PIN PACKAGE
PIN CONFIGURATIONS
ORDERING CODE
Philips Semiconductors
80-Pin Plastic Low Profile Quad Flat Pack (LQFP)
68-Pin Plastic Leaded Chip Carrier (PLCC)
23
22
21
20
19
18
17
16
15
14
13
12
10
11
Quad UART for 3.3 V and 5 V supply voltage
9
8
7
6
5
4
3
2
1
TxDb
RxDb
I/O3b
I/O2b
Vss_ic
Vcc_i
Vcc_o
I/O1b
I/O0b
TxDa
RxDa
Vss_o
I/O3a
I/O2a
I/O1a
I/O0a
DACKN
CEN
A0
W_RN
Vcc_i
Vcc_c
Vss_ic
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
26
10
PACKAGES
27
9
D0
Vss_o
Gout1
I/O3d
Gout0
I/O2d
I/O1d
I/O0d
Gin1
Gin0
RESETN
Vss_ic
Vcc_i
Vcc_c
TxDd
RxDd
TxDc
RxDc
I/O3c
I/O2c
Vss_o
I/O1c
I/O0c
68-Pin PLCC
TOP VIEW
1
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
43
61
44
60
SClk
A1
A2
A3
A4
A5
A7
X2
X1
VSS_O
IACKN
IRQN
D7
D6
VCC_I
VSS_IC
D5
D4
VCC_O
D3
D2
D1
Figure 1. Pin Configurations
3
4 Vss_ic, 4 Vcc_i, 4 Vss_o, 2 Vcc_o, 2Vcc_c
Pin Assignments
PINOUT - 80 PIN THIN PACKAGE
V
CC
= 3.3 V
±
10 %
20-23
SC28L194A1BE
Industrial
–40°C to +85°C
SC28L194A1A
27
26
25
24
19
18
17
16
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
RxDd
TxDc
nc
20
1
RxDc
I/O3c
I/O2c
I/O1c
I/O0c
TxDb
TxDa
Vss_o
RxDb
I/O3b
I/O2b
Vss_ic
Vcc_i
Vcc_o
I/O1b
I/O0b
RxDa
Vss_o
I/O3a
I/O2a
I/O1a
80
21
80-Pin LQFP
TOP VIEW
53
52
51
50
49
48
47
46
45
44
43
42
38
37
36
35
34
33
32
31
30
29
28
39-41
V
CC
= 5 V
±
10 %
SC28L194A1BE
Industrial
–40°C to +85°C
SC28L194A1A
Vcc_i
D5
D4
D3
D2
D1
D0
nc
Gin1
Gin0
Vcc_i
TxDd
61
40
Vss_ic
Vcc_o
Vss_o
Gout1
I/O3d
Gout0
I/O2d
I/O1d
I/O0d
Vss_ic
Vcc_c
41
60
RESETN
SD00544
78-80
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
60
59
58
57
56
55
54
61-62
SC28L194
Product data sheet
SOT315-1
SOT188-2
DWG #
nc
nc
I/O0a
CEN
A0
A1
A2
A3
A4
A5
A7
X2
X1
SClk
D7
D6
Vcc_i
DACKN
W_RN
Vcc_c
IRQN
Vss_o
Vss_ic
IACKN
Philips Semiconductors
Product data sheet
Quad UART for 3.3 V and 5 V supply voltage
SC28L194
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ÁÁÁÁÁÁÁÁ
MNEMONIC
TYPE
I
I
I
DESCRIPTION
SClk
Host system clock. Used to time operations in the Host Interface and clock internal logic. Must be greater than
twice the frequency of highest X1, Counter/Timer, TxC (1x) or RxC (1x) input frequency.
Chip select: Active low. When asserted, allows I/O access to QUART registers by host CPU. W_RN signal
indicates direction. (Must
not be active in IACKN cycle)
Address lines (A[6] is
NOT
used. See “Host Interface” )
8-bit bi-directional data bus. Carries command and status information between 28L194 and the host CPU.
Used to convey parallel data for serial I/O between the host CPU and the 28L194
CEN
A(7:0)
D(7:0)
I/O
I
W_RN
Write Read not control: When high indicates that the host CPU will write to a 28L194 register or transmit FIFO.
When low, indicates a read cycle. 0 = Read; 1 = Write
Data Acknowledge: Active low. When asserted, it signals that the last transfer of the D lines is complete.
Open drain requires a pull-up device.
Interrupt Request: Active low. When asserted, indicates that the 28L194 requires service for pending
interrupt(s).
Open drain requires a pull-up device.
DACKN
IRQN
O
O
I
IACKN
Interrupt Acknowledge: Active low. When asserted, indicates that the host CPU has initiated an interrupt
acknowledge cycle.
(Do not use CEN in an IACKN cycle)
Transmit Data: Serial outputs from the 4 UARTs.
Receive Data: Serial inputs to the 4 UARTs
TD(a-d)
O
I
RD(a-d)
I/O0(a-d)
I/O1(a-d)
I/O2(a-d)
I/O3(a-d)
Gin(1:0)
I/O
I/O
I/O
I/O
I
I
I
O
Input/Output 0: Multi-use input or output pin for the UART.
Input/Output 1: Multi-use input or output pin for the UART.
Input/Output 2: Multi-use input or output pin for the UART.
Input/Output 3: Multi-use input or output pin for the UART.
Global general purpose inputs, available to any/all channels.
Global general purpose outputs, available from any channel.
Gout(1:0)
RESETN
Master reset: Active Low. Must be asserted at power up and may be asserted at other times to reset and
restart the system.
See “Reset Conditions” at end of register map.
Minimum width 10 SCLK.
Crystal 1 or Communication Clock: This pin may be connected to one side of a 2-8 MHz crystal. It may
alternatively be driven by an external clock in this frequency range. Standard frequency = 3.6864 MHz
X1/CCLK
X2
O
I
Crystal 2: If a crystal is used, this is the connection to the second terminal. If a clock signal drives X1, this pin
must be left unconnected.
16 pins total 8 pins for Vss, 8 pins for Vcc
Power Supplies
NOTE:
1. Many output pins will have very fast edges, especially when lightly loaded (less than 20 pf). These edges may move as fast as 1 to 3 ns fall
or rise time. The user must be aware of the possible generation of ringing and reflections on improperly terminated interconnections. See
previous note on Sclk noise under pin assignments.
Pin Description
ÁÁÁÁÁ
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Á
Á
SYMBOL
T
amb
T
stg
V
CC
V
SS
PD
PD
PARAMETER
RATING
UNIT
°C
°C
V
V
Operating ambient temperature
Storage temperature range
Voltage from V
DD
to V
SS4
range
2
See Note 3
-65 to +150
-0.5 to +7.0
2.87
2
23
16
Voltage from any pin to V
SS
-0.5 to V
CC
+ 0.5
Package Power Dissipation (PLCC)
Package Power Dissipation (LQFP)
W
W
Derating factor above 25°C (PLCC package)
Derating factor above 25°C (LQFP package)
mW/°C
mW/°C
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
the functional operation of the device at these or any other conditions above those indicated in the Operation Section of this specification is
not implied.
2. For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature.
3. Parameters are valid over specified temperature range. See Ordering Information table for applicable temperature range and operating
supply range.
4. This product includes circuitry specifically designed for the protewction of its internal devices from damaging effects of excessive static
charge.
2006 Aug 15
4
ABSOLUTE MAXIMUM RATINGS
1
Philips Semiconductors
Product data sheet
Quad UART for 3.3 V and 5 V supply voltage
SC28L194
BLOCK DIAGRAM
FULL DUPLEX UART CHANNEL
INTERRUPT ARBITRATION
DATA DRIVERS AND MODEM INTERFACE
TIMING AND BAUD RATE
GENERATOR
I/O PORT TIMING AND
INTERFACE
HOST INTERFACE
FULL DUPLEX UART CHANNEL
FULL DUPLEX UART CHANNEL
FULL DUPLEX UART CHANNEL
INPUT BUFFERS AND OUTPUT DRIVERS
Block Diagram SC28L194
Figure 2. Block Diagram
As shown in the block diagram, the Quad UART consists of an
interrupt arbiter, host interface, timing blocks and four UART channel
blocks. The four channels blocks operate independently, interacting
only with the timing, host I/F and interrupt blocks.
SD00524
Asynchronous bus cycle
The asynchronous mode requires one bus cycle of the chip select
(CEN) for each read or write to the chip. No more action will occur
on the bus after the C4 time until CEN is returned high.
Synchronous bus cycle
In the synchronous mode a read or write will be done every four
cycles of the Sclk. CEN does not require cycling but must remain
low to keep the synchronous accesses active. This provides a burst
mode of access to the chip.
In both cases each read or write operation(s) will be completed in
four (4) Sclk cycles. The difference in the two modes is only that the
asynchronous mode will not begin another bus cycle if the CEN
remains active after the four internal Sclk have completed. Internally
the asynchronous cycle will terminate after the four periods of Sclk
regardless of how long CEN is held active
In all cases the internal action will terminate at the withdrawal of
CEN. Synchronous CEN cycles shorter than multiples of four Sclk
cycles minus 1 Sclk and asynchronous CEN cycles shorter than four
Sclk cycles may cause short read or write cycles and produce
corrupted data transfers.
FUNCTIONAL DESCRIPTION
The SC28L194 is composed of several functional blocks:
•
Synchronous host interface block
•
A timing block consisting of a common baud rate generator
•
4 identical independent full duplex UART channel blocks
•
Interrupt arbitration system evaluating 24 contenders
•
I/O port control section and change of state detectors.
CONCEPTUAL OVERVIEW
Host Interface
The Host interface is comprised of the signal pins CEN, W/RN,
IACKN, DACKN, IRQN Sclk and provides all the control for data
transfer between the external and internal data buses of the host
and the QUART. The host interface operates in a synchronous mode
with the system (Sclk) which has been designed for a nominal
operating frequency of 33 MHz. The interface operates in either of
two modes;
synchronous
or
asynchronous
to the Sclk However
the bus cycle within the QUART
always
takes place in four Sclk
cycles after CEN is recognized. These four cycles are the C1, C2,
C3, C4 periods shown in the timing diagrams. DACKN always
occurs in the C4 time and occurs approximately 18 ns after the
rising edge of C4.
Addressing of the various functions of the QUART is through the
address bus A(7:0). To maintain upward compatibility with the
SC28L/C198 Octart the 8 bit address is still defined as such.
However A(6) is NOT used and is internally connected to Vss
(ground). The pin is, therefore, not included in the pin diagram. The
address space is controlled by A(5:0) and A(7). A[7], in a general
sense, is used to separate the data portion of the circuit from the
control portion.
2006 Aug 15
5
making 22 industry standard baud rates and 2 16-bit counters
used for non-standard baud rate generation
Timing Circuits
The timing block consists of a crystal oscillator, a fixed baud rate
generator (BRG), a pair of programmable 16 bit register based
counters. A buffer for the System Clock generates internal timing for
processes not directly concerned with serial data flow.
Crystal Oscillator
The crystal oscillator operates directly from a crystal, tuned between
1.0 and 8.0 MHz, connected across the X1/CCLK and X2 inputs with
a minimum of external components. BRG values listed for the clock
select registers correspond to a 3.6864 MHz crystal frequency. Use
of a 7.3728 MHz crystal will double the Communication Clock
frequencies.
An external clock in the 100 KHz to 10 MHz frequency range may
be connected to X1/CCLK. If an external clock is used instead of a
crystal, X1/CCLK
must
be driven and X2 left floating. The X1 clock
serves as the basic timing reference for the baud rate generator
(BRG) and is available to the BRG timers. The X1 oscillator input
MCU
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