NCP81075
High Performance Dual
MOSFET Gate Driver
Introduction
8
1
SOIC−8 NB
CASE 751−07
Features
•
Drives Two N-Channel MOSFETs in High-Side and Low-Side
•
•
•
•
•
•
•
•
•
•
•
•
•
Configuration
Floating Top Driver Accommodates Boost Voltage up to 180 V
Switching Frequency up to 1 MHz
20 ns Propagation Delay Times
4 A Sink, 4 A Source Output Currents
8 ns Rise / 7 ns Fall Times with 1000 pF Load
UVLO Protection
Specified from −40°C to 140°C
Offered in SOIC−8 (D), DFN8 (MN), WDFN10 (MT)
Packages
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Telecom and Datacom
Isolated Non−Isolated Power Supply Architectures
Class D Audio Amplifiers
Two Switch and Active Clamp Forward Converters
8
MARKING DIAGRAMS
NCP81075
ALYWG
G
1
NCP81075 = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
NCP
81075
ALYWG
G
PINOUT DIAGRAMS
VDD 1
HB 2
HO 3
HS 4
8 LO
7 VSS
6 LI
5 HI
VDD 1
HB 2
HO 3
HS 4
NC 5
WDFN10
NCP81075
(top views)
10 LO
9 VSS
8 LI
7 HI
6 NC
Applications
Simplified Application Diagram
SOIC/DFN8
VDD
VDD
HB
HI
HO
VIN
ORDERING INFORMATION
Device
VOUT
PWM
CONTROLLER
LI
NCP81075
HS
LO
VSS
NCP81075DR2G
NCP81075MNTXG
NCP81075MTTXG
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2016
1
October, 2017 − Rev. 1
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1
The NCP81075 is a high performance dual MOSFET gate driver
optimized to drive the gates of both high and low side power
MOSFETs in a synchronous buck converter. The NCP81075 uses an
on−chip bootstrap diode to eliminate the external discrete diode. A
high floating top driver design can accommodate HB voltage as high
as 180 V. The low−side and high−side are independently controlled
and match to 4 ns between the turn−on and turn−off of each other.
Independent Under−Voltage lockout is provided for the high side and
low side driver forcing the output low when the drive voltage is below
a specific threshold.
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1
DFN8
CASE 506CY
WDFN10
CASE 511CE
Package
SOIC8
(Pb−Free)
DFN8
(Pb−Free)
WDFN10
(Pb−Free)
Shipping
†
2500 /
Tape & Reel
4000 /
Tape & Reel
4000 /
Tape & Reel
Publication Order Number:
NCP81075/D
NCP81075
Table 1. PIN DESCRIPTION
Pin No.
SOIC/DFN8
1
2
3
4
5
6
7
8
−
Pin No.
WDFN10
1
2
3
4
7
8
9
10
5,6
Symbol
VDD
HB
HO
HS
HI
LI
VSS
LO
NC
Description
Positive Supply to the Lower Gate Driver
High Side Bootstrap Supply
High Side Output
High−Side Source
High−Side Input
Low−Side Input
Negative Supply Return
Low−Side Output
No Connect
Table 2. MAXIMUM RATINGS
Parameter
VDD
V
HB
V
HO
DC
Repetitive Pulse < 100 ns
V
HS
V
LO
DC
DC
Repetitive pulse < 100 ns
V
HI
, V
LI
V
HB − HS
Operating Junction Temperature Range, T
J
Storage Temperature, T
STG
Lead Temperature (Soldering, 10 sec)
HBM
CDM
Value
−0.3 to 24
−0.3 to 200
V
HS
– 0.3 to V
HB
+ 0.3
V
HS
− 2 to V
HB
+ 0.3, (V
HB
− V
HS
< 24)
−20 to 200 − VDD
−0.3 to VDD + 0.3
−2 to VDD + 0.3
−10 to 24
−0.3 to 24
−40 to 170
−65 to 150
+300
1000
2000
V
V
°C
°C
°C
V
V
V
V
Units
V
V
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. V
HB
– V
HS
should be in the range of −0.3 V to +20 V.
Table 3. RECOMMENDED OPERATING CONDITIONS
Parameter
V
DD
V
HS
V
HB
Supply Voltage Range
Voltage on HS (DC)
Voltage on HB
Voltage Slew Rate on HS
T
J
V
HO
V
LO
Operating Junction Temperature Range
−40
V
HS
− 0.3
−0.3
Min
8.5
−10
V
HS
+ 8,
V
DD
− 1
Nom
12
Max
20
180 − VDD
V
HS
+ 20,
180
50
+140
V
HB
+ 0.3
V
DD
+ 0.3
V / ns
°C
V
V
Units
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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NCP81075
ABSOLUTE MAXIMUM RATINGS
Table 4. ELECTRICAL/THERMAL INFORMATION
(All signals referenced to GND unless noted otherwise, Note 2)
Thermal Characteristic
q
JA
Junction to Ambient thermal resistance
q
JC(top)
Junction to case (Top) thermal resistance
q
JB
Junction to Board thermal resistance
q
JC(Bottom)
Junction to case (Bottom) thermal resistance
y
JT
Junction to top characterization parameter
y
JB
Junction to board characterization parameter
Moisture Sensitivity Level (MSL)
QFN Package
2. This data was taken using the JEDEC proposed High−K Test PCB.
SOIC
41
50
10
1.5
3.1
10
DFN8
36
42
19.1
4
0.6
19.3
1
DFN10
35
32
12
1.3
0.2
12.2
Unit
°C/W
Table 5. ELECTRICAL CHARACTERISTICS
Unless otherwise stated: T
A
= T
J
= −40°C to 140°C; VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HO
Parameter
SUPPLY CURRENTS
I
DD
I
DDO
VDD quiescent current
VDD operating current
V
LI
= V
HI
= 0
f = 500 kHz, C
LOAD
= 0
f = 300 kHz, C
LOAD
= 0
I
HB
I
HBO
Boot voltage quiescent current
Boot voltage operating current
V
LI
= V
HI
= 0 V
f = 500 kHz, C
LOAD
= 0
f = 300 kHz, C
LOAD
= 0
I
HBS
I
HBSO
INPUT
V
HIH
, V
LIH
V
HIL
, V
LIL
R
IN
Input rising threshold
Input falling threshold
Input Pulldown Resistance
100
170
2.7
0.8
350
kW
V
HB to V
SS
quiescent current
HB to V
SS
operating current
V
HS
= V
HB
= 110 V
f = 500 kHz, C
LOAD
= 0
0.85
7.3
4.9
0.92
6.55
4.5
5.0
0.1
1.8
15
11
1.8
12
7.0
25
mA
mA
mA
Test Condition
Min
Typ
Max
Units
UNDERVOLTAGE PROTECTION (UVLO)
VDD rising threshold
VDD threshold hysteresis
VHB rising threshold
VHB threshold hysteresis
BOOTSTRAP DIODE
V
F
V
FI
R
D
Low−current forward voltage
High−current forward voltage
Dynamic resistance,
DVF/DI
I
VDD
− HB = 100
mA
I
VDD
− HB = 100 mA
I
VDD
− HB = 100 mA and 80 mA
0.59
0.85
0.94
0.95
1.1
2.0
W
V
5.5
6.2
7.1
0.58
6.5
0.5
7.5
8.0
V
LO GATE DRIVER
V
LOL
V
LOH
Low level output voltage
High level output voltage
Peak pull−up current
Peak pull−down current
I
LO
= 100 mA
I
LO
= −100 mA, V
LOH
= V
DD
− V
LO
V
LO
= 0 V
V
LO
= 12 V
0.1
0.15
4
4
0.40
0.40
A
V
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NCP81075
Table 5. ELECTRICAL CHARACTERISTICS
Unless otherwise stated: T
A
= T
J
= −40°C to 140°C; VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HO
Parameter
HO GATE DRIVER
V
HOL
V
HOH
Low level output voltage
High level output voltage
Peak pull−up current
Peak pull−down current
PROPAGATION DELAYS
t
DLFF
V
LI
falling to V
LO
falling
C
LOAD
= 0 (−40 to 125°C)
C
LOAD
= 0 (−40 to 140°C)
t
DHFF
V
HI
falling to V
HO
falling
C
LOAD
= 0 (−40 to 125°C)
C
LOAD
= 0 (−40 to 140°C)
t
DLRR
V
LI
rising to V
LO
rising
C
LOAD
= 0 (−40 to 125°C)
C
LOAD
= 0 (−40 to 140°C)
t
DHRR
V
HI
rising to V
HO
rising
C
LOAD
= 0 (−40 to 125°C)
C
LOAD
= 0 (−40 to 140°C)
DELAY MATCHING
tMON
tMOFF
LI ON, HI OFF
LI OFF, HI ON
3.5
3.5
14
14
ns
20
20
20
20
20
20
20
20
45
50
45
50
45
50
45
50
ns
I
HO
= 100 mA
I
HO
= −100 mA, V
HOH
= V
HB
– V
HO
V
LO
= 0 V
V
LO
= 12 V
0.1
0.15
4
4
0.40
0.40
A
V
Test Condition
Min
Typ
Max
Units
OUTPUT RISE AND FALL TIME
t
R
t
F
t
R
t
F
LO, HO
LO, HO
LO, HO (3 V to 9 V)
LO, HO (3 V to 9 V)
C
LOAD
= 1000 pF
C
LOAD
= 1000 pF
C
LOAD
= 0.1
mF
C
LOAD
= 0.1
mF
8
7
0.2
0.25
0.55
0.45
ms
ns
MISCELLANEOUS
t
1
t
2
Minimum input pulse width that
changes the output
Bootstrap diode turn−off time
I
F
= 100 mA, I
REV
= −100 mA
(Notes 3 and 4)
30
50
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Typical values for T
A
= 25°C
4. I
F
: Forward current applied to bootstrap diode, I
REV
: Reverse current applied to bootstrap diode.
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NCP81075
Internal Block Diagram
Figure 1. Internal Block Diagram
Timing Diagrams
VDD / VHB-VHS
UVLO
Thresholds
LI
Delay ~ 40us
LO
HI
Delay ~ 40us
HO
Note: If HI is set and the High−Side driver (VHB−VHS) crosses its UVLO threshold
100ns after the VDD UVLO then a rising edge on HI is required to pull HO High.
Figure 2. UVLO
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