74LVCH16245AEV/G:5 datasheet, PDF

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74LVCH16245AEV/G:5: DescriptionIC TXRX NON-INVERT 3.6V 56VFBGA; Categorylogic logic; File Size819KB，20 Pages; ManufacturerNexperia; Websitehttps://www.nexperia.com

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74LVCH16245AEV/G:5 Overview

IC TXRX NON-INVERT 3.6V 56VFBGA

74LVCH16245AEV/G:5 Parametric

Parameter Name	Attribute value
Brand Name	Nexperia
Maker	Nexperia
Parts packaging code	BGA
package instruction	VFBGA-56
Contacts	56
Manufacturer packaging code	SOT702-1
Reach Compliance Code	compliant
Other features	WITH DIRECTION CONTROL
series	LVC/LCX/Z
JESD-30 code	R-PBGA-B56
length	7 mm
Logic integrated circuit type	BUS TRANSCEIVER
Humidity sensitivity level	2
Number of digits	8
Number of functions	2
Number of ports	2
Number of terminals	56
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	240
propagation delay (tpd)	5.5 ns
Certification status	Not Qualified
Maximum seat height	0.97 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	1.2 V
Nominal supply voltage (Vsup)	2.7 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal form	BALL
Terminal pitch	0.65 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	20
width	4.5 mm

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74LVC16245A; 74LVCH16245A

16-bit bus transceiver with direction pin; 5 V tolerant; 3-state

Rev. 12 — 13 February 2012

Product data sheet

1. General description

The 74LVC16245A; 74LVCH16245A are 16-bit transceivers featuring non-inverting

3-state bus compatible outputs in both send and receive directions. The device features

two output enable (nOE) inputs for easy cascading and two send/receive (nDIR) inputs for

direction control. nOE controls the outputs so that the buses are effectively isolated. This

device can be used as two 8-bit transceivers or one 16-bit transceiver.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be

applied to the outputs. These features allow the use of these devices in mixed

3.3 V and 5 V applications.

The 74LVCH16245A bus hold on data inputs eliminates the need for external pull-up

resistors to hold unused inputs.

2. Features and benefits



5 V tolerant inputs/outputs for interfacing with 5 V logic

Wide supply voltage range from 1.2 V to 3.6 V

CMOS low power consumption

MULTIBYTE flow-through standard pin-out architecture

Low inductance multiple power and ground pins for minimum noise and ground

bounce

Direct interface with TTL levels

High-impedance when V

= 0 V

All data inputs have bus hold (74LVCH16245A only)

Complies with JEDEC standard:



JESD8-7A (1.65 V to 1.95 V)



JESD8-5A (2.3 V to 2.7 V)



JESD8-C/JESD36 (2.7 V to 3.6 V)

ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-B exceeds 200 V



CDM JESD22-C101E exceeds 1000 V

Specified from

40 C

to +85

C

and

40 C

to +125

C



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