Jitter Attenuator
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016
ICS874003D-02
DATA SHEET
General Description
The ICS874003D-02 is a high performance Differential-to-LVDS
Jitter Attenuator. In some PCI Express systems, such as those found
in desktop PCs, the PCI Express clocks are generated from a low
bandwidth, high phase noise PLL frequency synthesizer. In these
systems, a jitter attenuator may be required to attenuate high
frequency random and deterministic jitter components from the PLL
synthesizer and from the system board. The ICS874003D-02 has a
bandwidth of 3MHz. The 3MHz provides an intermediate bandwidth
that can easily track triangular spread profiles, while providing good
jitter attenuation.
The ICS874003D-02 uses IDT’s 3
rd
Generation FemtoClock
®
PLL
technology to achieve the lowest possible phase noise. The device is
packaged in a 20-Lead TSSOP package, making it ideal for use in
space constrained applications such as PCI Express add-on cards.
Features
•
•
•
•
•
•
•
•
•
•
•
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Three differential LVDS output pairs
One differential clock input
CLK, nCLK can accept the following differential input levels:
LVPECL, LVDS, HCSL
Input frequency range: 98MHz to 128MHz
Output frequency range: 98MHz to 320MHz
VCO range: 490MHz - 640MHz
Cycle-to-Cycle jitter: 30ps (maximum)
3MHz PLL loop bandwidth
0°C to 70°C ambient operating temperature
Full 3.3V operating supply
Lead-free (RoHS 6) packaging
For drop-in replacement use 874003AG-02
F_SEL[2:0] Function Table
Inputs
F_SEL2
0
1
0
1
0
1
0
1
F_SEL1
0
0
1
1
0
0
1
1
F_SEL0
0
0
0
0
1
1
1
1
Outputs
QA[0:1],
nQA[0:1]
÷2 (default)
÷5
÷4
÷2
÷2
÷5
÷4
÷4
QB0, nQB0
÷2 (default)
÷2
÷2
÷4
÷5
÷4
÷5
÷4
Pin Assignment
QA1
V
DDO
QA0
nQA0
MR
F_SEL0
nc
V
DDA
F_SEL1
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
nQA1
V
DDO
QB0
nQB0
F_SEL2
OEB
GND
nCLK
CLK
OEA
ICS874003D-02
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm package body
G Package
Top View
ICS874003DG-02 REVISION A MARCH 11, 2016
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©2016 Integrated Device Technology, Inc.
ICS874003D-02 Data Sheet
JITTER ATTENUATOR
Block Diagram
OEA
F_SEL2:0
Pullup
Pulldown
3
QA0
÷5
÷4
÷2
(default)
Pulldown
nQA0
QA1
CLK
nCLK
Pullup
Phase
Detector
VCO
490 - 640MHz
3
nQA1
M = ÷5
(fixed)
÷5
÷4
÷2
(default)
QB0
nQB0
MR
Pulldown
OEB
Pullup
ICS874003DG-02 REVISION A MARCH 11, 2016
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©2016 Integrated Device Technology, Inc.
ICS874003D-02 Data Sheet
JITTER ATTENUATOR
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1, 20
2, 19
3, 4
Name
QA1, nQA1
V
DDO
QA0, nQA0
Output
Power
Output
Type
Description
Differential output pair. LVDS interface levels.
Output supply pins.
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs (Qx) to go low and the inverted outputs (nQx) to go
high. When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
Frequency select pin for QAx, nQAx and QB0, nQB0 outputs.
LVCMOS/LVTTL interface levels.
No connect.
Analog supply pin.
Core supply pin.
Pullup
Pulldown
Pullup
Output enable pin for QAx pins. When HIGH, the QAx, nQAx outputs are
active. When LOW, the QAx, nQAx outputs are in a high impedance state.
LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
Power supply ground.
Pullup
Output enable pin for QB0 pins. When HIGH, the QB0, nQB0 outputs are
active. When LOW, the QB0, nQB0 outputs are in a high impedance state.
LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
5
MR
Input
Pulldown
6,
9,
16
7
8
10
11
12
13
14
15
17, 18
F_SEL0,
F_SEL1,
F_SEL2
nc
V
DDA
V
DD
OEA
CLK
nCLK
GND
OEB
nQB0, QB0
Input
Unused
Power
Power
Input
Input
Input
Power
Input
Output
Pulldown
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
Function Table
Table 3. Output Enable Function Table
Inputs
OEA
0
1
OEB
0
1
Outputs
QA[0:1], nQA[0:1]
Hi-Impedance
Enabled
QB0, nQB0
Hi-Impedance
Enabled
ICS874003DG-02 REVISION A MARCH 11, 2016
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©2016 Integrated Device Technology, Inc.
ICS874003D-02 Data Sheet
JITTER ATTENUATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the
DC Characteristics or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
86.7°C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.15
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
DD
3.465
80
15
75
Units
V
V
V
mA
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
OEA, OEB
Input High
Current
MR,
F_SEL[2:0]
OEA, OEB
I
IL
Input Low
Current
MR,
F_SEL[2:0]
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
ICS874003DG-02 REVISION A MARCH 11, 2016
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©2016 Integrated Device Technology, Inc.
ICS874003D-02 Data Sheet
JITTER ATTENUATOR
Table 4C. Differential DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
I
IH
Parameter
Input High
Current
Input Low
Current
CLK
nCLK
CLK
nCLK
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
0.15
GND + 0.5
1.3
V
DD
– 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
I
IL
V
PP
V
CMR
Peak-to-Peak Voltage;
NOTE 1
Common Mode Input
Voltage; NOTE 1, 2
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
Table 4D. LVDS DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
OD
V
OD
V
OS
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.2
1.35
Test Conditions
Minimum
275
Typical
375
Maximum
485
50
1.5
50
Units
mV
mV
V
mV
Table 5. AC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
f
OUT
tjit(cc)
tsk(o)
tsk(b)
t
R
/ t
F
odc
Parameter
Output Frequency
Cycle-to-Cycle Jitter; NOTE 1
Output Skew; NOTE 2, 3
Bank Skew; NOTE 1, 4
Output Rise/Fall Time
Output Duty Cycle
Bank A
20% to 80%
250
47
Test Conditions
Minimum
98
Typical
Maximum
320
30
185
65
700
53
Units
MHz
ps
ps
ps
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoints.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.
ICS874003DG-02 REVISION A MARCH 11, 2016
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©2016 Integrated Device Technology, Inc.
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