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74HCT259PW-Q100,11

Description
IC LATCH 8BIT ADDRESS 16TSSOP
Categorylogic    logic   
File Size821KB,20 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
Download Datasheet Parametric Compare View All

74HCT259PW-Q100,11 Overview

IC LATCH 8BIT ADDRESS 16TSSOP

74HCT259PW-Q100,11 Parametric

Parameter NameAttribute value
Brand NameNexperia
MakerNexperia
Parts packaging codeTSSOP
package instructionTSSOP,
Contacts16
Manufacturer packaging codeSOT403-1
Reach Compliance Codecompliant
Samacsys Description74HC(T)259-Q100 - 8-bit addressable latch@en-us
Other features1:8 DMUX FOLLOWED BY LATCH
seriesHCT
JESD-30 codeR-PDSO-G16
JESD-609 codee4
length5 mm
Logic integrated circuit typeD LATCH
Humidity sensitivity level1
Number of digits1
Number of functions1
Number of terminals16
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
propagation delay (tpd)57 ns
Filter levelAEC-Q100
Maximum seat height1.1 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typeLOW LEVEL
width4.4 mm
Base Number Matches1
74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
Rev. 1 — 30 July 2012
Product data sheet
1. General description
The 74HC259-Q100; 74HCT259-Q100 are high-speed Si-gate CMOS devices and are pin
compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7A.
The 74HC259-Q100; 74HCT259-Q100 are high-speed 8-bit addressable latches
designed for general-purpose storage applications in digital systems. They are
multifunctional devices capable of storing single-line data in eight addressable latches and
providing a 3-to-8 decoder and multiplexer function with active HIGH outputs (Q0 to Q7).
They also incorporate an active LOW common reset (MR) for resetting all latches as well
as an active LOW enable input (LE).
The 74HC259-Q100; 74HCT259-Q100 has four modes of operation:
Addressable latch mode, in this mode data on the data line (D) is written into the
addressed latch. The addressed latch follows the data input with all non-addressed
latches remaining in their previous states.
Memory mode, in this mode all latches remain in their previous states and are
unaffected by the data or address inputs.
Demultiplexing mode (or 3-to-8 decoding), in this mode the addressed output follows
the state of the data input (D) with all other outputs in the LOW state.
Reset mode, in this mode all outputs are LOW and unaffected by the address inputs
(A0 to A2) and data input (D).
When operating the 74HC259-Q100; 74HCT259-Q100 as an address latch, changing
more than one address bit could impose a transient wrong address. Therefore, this should
only be done while in the Memory mode.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Combined demultiplexer and 8-bit latch
Serial-to-parallel capability
Output from each storage bit available
Random (addressable) data entry
Easily expandable
Common reset input

74HCT259PW-Q100,11 Related Products

74HCT259PW-Q100,11 74HCT259D-Q100,118 74HC259BQ-Q100,115 74HC259D-Q100,118 74HC259PW-Q100,118 935298822118 935298821115 935298826118
Description IC LATCH 8BIT ADDRESS 16TSSOP IC LATCH 8BIT ADDRESS 16SOIC IC LATCH 8BIT ADDRESS 16DHVQFN IC LATCH 8BIT ADDRESS 16SOIC IC LATCH 8BIT ADDRESS 16TSSOP IC LATCH 8BIT ADDRESS 16SOIC IC LATCH 8BIT ADDRESS 16DHVQFN IC LATCH 8BIT ADDRESS 16TSSOP
package instruction TSSOP, SOP-16 DHVQFN-16 SOP-16 TSSOP-16 SOP, DHVQFN-16 TSSOP-16
Reach Compliance Code compliant compliant compliant compliant compliant compliant compliant compliant
series HCT HCT HC/UH HC/UH HC/UH HC/UH HC/UH HCT
JESD-30 code R-PDSO-G16 R-PDSO-G16 R-PQCC-N16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PQCC-N16 R-PDSO-G16
length 5 mm 9.9 mm 3.5 mm 9.9 mm 5 mm 9.9 mm 3.5 mm 5 mm
Logic integrated circuit type D LATCH D LATCH D LATCH D LATCH D LATCH D LATCH D LATCH D LATCH
Number of digits 1 1 1 1 1 1 1 1
Number of functions 1 1 1 1 1 1 1 1
Number of terminals 16 16 16 16 16 16 16 16
Maximum operating temperature 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C
Output polarity TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP SOP HVQCCN SOP TSSOP SOP HVQCCN TSSOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE SMALL OUTLINE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
propagation delay (tpd) 57 ns 57 ns 255 ns 255 ns 255 ns 255 ns 255 ns 57 ns
Filter level AEC-Q100 AEC-Q100 AEC-Q100 AEC-Q100 AEC-Q100 AEC-Q100 AEC-Q100 AEC-Q100
Maximum seat height 1.1 mm 1.75 mm 1 mm 1.75 mm 1.1 mm 1.75 mm 1 mm 1.1 mm
Maximum supply voltage (Vsup) 5.5 V 5.5 V 6 V 6 V 6 V 6 V 6 V 5.5 V
Minimum supply voltage (Vsup) 4.5 V 4.5 V 2 V 2 V 2 V 2 V 2 V 4.5 V
Nominal supply voltage (Vsup) 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V
surface mount YES YES YES YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE
Terminal form GULL WING GULL WING NO LEAD GULL WING GULL WING GULL WING NO LEAD GULL WING
Terminal pitch 0.65 mm 1.27 mm 0.5 mm 1.27 mm 0.65 mm 1.27 mm 0.5 mm 0.65 mm
Terminal location DUAL DUAL QUAD DUAL DUAL DUAL QUAD DUAL
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
Trigger type LOW LEVEL LOW LEVEL LOW LEVEL LOW LEVEL LOW LEVEL LOW LEVEL LOW LEVEL LOW LEVEL
width 4.4 mm 3.9 mm 2.5 mm 3.9 mm 4.4 mm 3.9 mm 2.5 mm 4.4 mm
Brand Name Nexperia Nexperia Nexperia Nexperia Nexperia - - -
Maker Nexperia Nexperia Nexperia Nexperia Nexperia - Nexperia -
Parts packaging code TSSOP SOP QFN SOP TSSOP - - -
Contacts 16 16 16 16 16 - - -
Manufacturer packaging code SOT403-1 SOT109-1 SOT763-1 SOT109-1 SOT403-1 - - -
Samacsys Description 74HC(T)259-Q100 - 8-bit addressable latch@en-us 74HC(T)259-Q100 - 8-bit addressable latch@en-us 74HC(T)259-Q100 - 8-bit addressable latch@en-us 74HC(T)259-Q100 - 8-bit addressable latch@en-us 74HC(T)259-Q100 - 8-bit addressable latch@en-us - - -
Other features 1:8 DMUX FOLLOWED BY LATCH 1:8 DMUX FOLLOWED BY LATCH 1:8 DMUX FOLLOWED BY LATCH 1:8 DMUX FOLLOWED BY LATCH 1:8 DMUX FOLLOWED BY LATCH - - -
JESD-609 code e4 e4 e4 e4 e4 - e4 e4
Humidity sensitivity level 1 1 1 1 1 - 1 1
Terminal surface Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag) Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag) Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag) Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag) - Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag) Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)
Base Number Matches 1 1 1 1 1 1 - -
Is it Rohs certified? - conform to - conform to conform to conform to conform to conform to
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