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74LVC273BQ-Q100X

Description
IC FF D-TYPE SNGL 8BIT 20DHVQFN
Categorylogic    logic   
File Size693KB,16 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
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74LVC273BQ-Q100X Overview

IC FF D-TYPE SNGL 8BIT 20DHVQFN

74LVC273BQ-Q100X Parametric

Parameter NameAttribute value
Brand NameNexperia
MakerNexperia
Parts packaging codeQFN
package instructionHVQCCN,
Contacts20
Manufacturer packaging codeSOT764-1
Reach Compliance Codecompliant
Samacsys Description74LVC273-Q100 - Octal D-type flip-flop with reset; positive-edge trigger@en-us
seriesLVC/LCX/Z
JESD-30 codeR-PQCC-N20
length4.5 mm
Logic integrated circuit typeD FLIP-FLOP
Number of digits8
Number of functions1
Number of terminals20
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeHVQCCN
Package shapeRECTANGULAR
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
propagation delay (tpd)22.2 ns
Filter levelAEC-Q100
Maximum seat height1 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)1.65 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Trigger typePOSITIVE EDGE
width2.5 mm
minfmax150 MHz
74LVC273-Q100
Octal D-type flip-flop with reset; positive-edge trigger
Rev. 1 — 16 September 2013
Product data sheet
1. General description
The 74LVC273-Q100 has eight edge-triggered, D-type flip-flops with individual Dn inputs
and Qn outputs. The common clock (CP) and master reset (MR) inputs load and reset
(clear) all flip-flops simultaneously. The state of each Dn input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the
flip-flop. All outputs are forced LOW independent of clock or data inputs by a LOW voltage
level on the MR input.
The device is useful for applications where the true output only is required and the clock
and master reset are common to all storage elements.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Wide supply voltage range from 1.2 V to 3.6 V
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Output drive capability 50
transmission lines at +85
C
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)

74LVC273BQ-Q100X Related Products

74LVC273BQ-Q100X 74LVC273PW-Q100J 74LVC273D-Q100J
Description IC FF D-TYPE SNGL 8BIT 20DHVQFN IC FF D-TYPE SNGL 8BIT 20TSSOP IC FF D-TYPE SNGL 8BIT 20SO
Brand Name Nexperia Nexperia Nexperia
Maker Nexperia Nexperia Nexperia
Parts packaging code QFN TSSOP2 SOP
package instruction HVQCCN, TSSOP, SOP,
Contacts 20 20 20
Manufacturer packaging code SOT764-1 SOT360-1 SOT163-1
Reach Compliance Code compliant compliant compliant
Samacsys Description 74LVC273-Q100 - Octal D-type flip-flop with reset; positive-edge trigger@en-us 74LVC273-Q100 - Octal D-type flip-flop with reset; positive-edge trigger@en-us 74LVC273-Q100 - Octal D-type flip-flop with reset; positive-edge trigger@en-us
series LVC/LCX/Z LVC/LCX/Z LVC/LCX/Z
JESD-30 code R-PQCC-N20 R-PDSO-G20 R-PDSO-G20
length 4.5 mm 6.5 mm 12.8 mm
Logic integrated circuit type D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP
Number of digits 8 8 8
Number of functions 1 1 1
Number of terminals 20 20 20
Maximum operating temperature 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C
Output polarity TRUE TRUE TRUE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code HVQCCN TSSOP SOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR
Package form CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE
propagation delay (tpd) 22.2 ns 22.2 ns 22.2 ns
Filter level AEC-Q100 AEC-Q100 AEC-Q100
Maximum seat height 1 mm 1.1 mm 2.65 mm
Maximum supply voltage (Vsup) 3.6 V 3.6 V 3.6 V
Minimum supply voltage (Vsup) 1.65 V 1.65 V 1.65 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V
surface mount YES YES YES
technology CMOS CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal form NO LEAD GULL WING GULL WING
Terminal pitch 0.5 mm 0.65 mm 1.27 mm
Terminal location QUAD DUAL DUAL
Trigger type POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE
width 2.5 mm 4.4 mm 7.5 mm
minfmax 150 MHz 150 MHz 150 MHz
Is it Rohs certified? - conform to conform to
Base Number Matches - 1 1

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