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LTC4313CMS8-1#PBF

Description
LTC4313 - 2-Wire Bus Buffers with High Noise Margin; Package: MSOP; Pins: 8; Temperature Range: 0°C to 70°C
File Size277KB,20 Pages
ManufacturerLinear ( ADI )
Websitehttp://www.analog.com/cn/index.html
Environmental Compliance
Download Datasheet Parametric View All

LTC4313CMS8-1#PBF Overview

LTC4313 - 2-Wire Bus Buffers with High Noise Margin; Package: MSOP; Pins: 8; Temperature Range: 0°C to 70°C

LTC4313CMS8-1#PBF Parametric

Parameter NameAttribute value
Brand NameLinear Technology
Is it Rohs certified?conform to
Objectid1056543377
Parts packaging codeMSOP
package instructionLEAD FREE, PLASTIC, MSOP-8
Contacts8
Manufacturer packaging codeMS8
Reach Compliance Codecompliant
Analog Integrated Circuits - Other TypesANALOG CIRCUIT
JESD-30 codeS-PDSO-G8
JESD-609 codee3
length3 mm
Humidity sensitivity level1
Number of functions1
Number of terminals8
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeSQUARE
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
Maximum seat height1.1 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)2.9 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width3 mm
LTC4313-1/LTC4313-2/
LTC4313-3
2-Wire Bus Buffers with
High Noise Margin
FeaTures
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DescripTion
The LTC
®
4313 is a hot swappable 2-wire bus buffer
that provides bidirectional buffering while maintain-
ing a low offset voltage and high noise margin up to
0.3 • V
CC
. The high noise margin allows the LTC4313 to be
interoperable with devices that drive a high V
OL
(>0.4V) and
allows multiple LTC4313s to be cascaded. The LTC4313-1
and LTC4313-2 support level translation between 3.3V and
5V busses. In addition to these voltages, the LTC4313-3
also supports level translation to 1.5V, 1.8V and 2.5V.
During insertion, the SDA and SCL lines are pre-charged to
1V to minimize bus disturbances. Connection is established
between the input and output after ENABLE is asserted
high and a stop bit or bus idle condition has been detected
on the SDA and SCL pins.
If both data and clock are not simultaneously high at least
once in 45ms, the input is disconnected from the output.
Up to 16 clock pulses are subsequently generated to free
the stuck bus. Rise time accelerators (RTAs) provide pull-up
currents on SDA and SCL rising edges to meet rise time
specifications in heavily loaded systems. The RTAs are
configured as slew limited switches in the LTC4313-1 and
2.5mA current sources in the LTC4313-2. The LTC4313-3
does not have RTAs.
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents, including 6356140, 6650174,
7032051, 7478286.
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Bidirectional Buffer Increases Fanout
High Noise Margin with V
IL
= 0.3•V
CC
Compatible with Non-Compliant I
2
C Devices That
Drive a High V
OL
Strong (LTC4313-1) and 2.5mA (LTC4313-2)
Rise Time Accelerator Current
Level Shift 1.5V, 1.8V, 2.5V, 3.3V and 5V Busses
Prevents SDA and SCL Corruption During Live Board
Insertion and Removal from Backplane
Stuck Bus Disconnect and Recovery
Compatible with I
2
C, I
2
C Fast Mode and SMBus
±4kV Human Body Model ESD Ruggedness
High Impedance SDA, SCL Pins When Unpowered
8-Lead MSOP and 8-Lead (3mm × 3mm) DFN
Packages
applicaTions
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Capacitance Buffers/Bus Extender
Live Board Insertion
Telecommunications Systems Including ATCA
Level Translation
PMBus
Servers
Typical applicaTion
3.3V
5V
400kHz Operation
R
BUS_IN
= 2.7k , C
BUS_IN
= 50pF
R
BUS_OUT
= 1.3k , C
BUS_OUT
= 100pF
0.01µF
2.7k
2.7k
V
CC
ENABLE
LTC4313-1
READY
10k
1.3k
1.3k
SCLOUT
1V/DIV
SCLIN
READY
SCL2
SDA2
500ns/DIV
4313123 TA01b
SCL1
SDA1
SCLIN
SDAIN
GND
SCLOUT
SDAOUT
4313123 TA01a
4313123f
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