28LV64A-20/P datasheet, PDF - EEWORLD Datasheet

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28LV64A-20/P: Description64K (8K x 8) Low Voltage CMOS EEPROM; Categorystorage storage; File Size48KB，8 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

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28LV64A-20/P Overview

64K (8K x 8) Low Voltage CMOS EEPROM

28LV64A-20/P Parametric

Parameter Name	Attribute value
Parts packaging code	DIP
package instruction	PLASTIC, DIP-28
Contacts	28
Reach Compliance Code	unknow
Maximum access time	200 ns
Other features	MINIMUM 100K WRITE/ERASE CYCLE; 200 YEAR DATA RETENTION
command user interface	NO
Data polling	YES
JESD-30 code	R-PDIP-T28
memory density	65536 bi
Memory IC Type	EEPROM
memory width	8
Number of functions	1
Number of terminals	28
word count	8192 words
character code	8000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	8KX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP28,.6
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
power supply	3/3.3 V
Programming voltage	3 V
Certification status	Not Qualified
ready/busy	YES
Maximum standby current	0.0001 A
Maximum slew rate	0.008 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
switch bit	NO
Maximum write cycle time (tWC)	3 ms
Base Number Matches	1

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28LV64A

64K (8K x 8) Low Voltage CMOS EEPROM

FEATURES

• 2.7V to 3.6V Supply

• Read Access Time—300 ns

• CMOS Technology for Low Power Dissipation

- 8 mA Active

- 50

A CMOS Standby Current

• Byte Write Time—3 ms

• Data Retention >200 years

• High Endurance - Minimum 100,000 Erase/Write

Cycles

• Automatic Write Operation

- Internal Control Timer

- Auto-Clear Before Write Operation

- On-Chip Address and Data Latches

• Data Polling

• Ready/Busy

• Chip Clear Operation

• Enhanced Data Protection

- V

Detector

- Pulse Filter

- Write Inhibit

• Electronic Signature for Device Identiﬁcation

• Organized 8Kx8 JEDEC Standard Pinout

- 28-pin Dual-In-Line Package

- 32-pin Chip Carrier (Leadless or Plastic)

- 28-pin Thin Small Outline Package (TSOP)

8x20mm

- 28-pin Very Small Outline Package (VSOP)

8x13.4mm

• Available for Extended Temperature Ranges:

- Commercial: 0˚C to +70˚C

- Industrial: -40˚C to +85˚C

PACKAGE TYPES

RDY/BSY

A12

I/O0

I/O1

I/O2

•1

Vcc

A11 A4

A10 A2

I/O7

I/O6

I/O0

I/O5

I/O4

I/O3

RDY/BSY

A12

Vcc

A11

A10

I/O7

I/O6

• Pin 1 indicator on PLCC on top of package

A11

Vcc

RDY/BSY

A12

A11

RDY/BSY

A12

DESCRIPTION

The Microchip Technology Inc. 28LV64A is a CMOS 64K non-vol-

atile electrically Erasable PROM organized as 8K words by 8 bits.

The 28LV64A is accessed like a static RAM for the read or write

cycles without the need of external components. During a “byte

write”, the address and data are latched internally, freeing the

microprocessor address and data bus for other operations. Fol-

lowing the initiation of write cycle, the device will go to a busy state

and automatically clear and write the latched data using an inter-

nal control timer. To determine when the write cycle is complete,

the user has a choice of monitoring the Ready/Busy output or

using Data polling. The Ready/Busy pin is an open drain output,

which allows easy conﬁguration in ‘wired-or’ systems. Alterna-

tively, Data polling allows the user to read the location last written

to when the write operation is complete. CMOS design and pro-

cessing enables this part to be used in systems where reduced

power consumption and reliability are required. A complete family

of packages is offered to provide the utmost ﬂexibility in applica-

tions.

BLOCK DIAGRAM

I/O0...................I/O7

VSS

VCC

Rdy/

Busy

A12

Data Protection

Circuitry

Chip Enable/

Output Enable

Control Logic

Auto Erase/Write

Timing

Program Voltage

Generation

Decoder

Data

Poll

Input/Output

Buffers

Decoder

1996 Microchip Technology Inc.

Preliminary

This document was created with FrameMaker 4 0 4

I/O1

I/O2

Vss

I/O3

I/O4

I/O5

Y Gating

64K bit

Cell Matrix

DS21113B-page 1

DIP/SOIC

PLCC/LCC

A10

I/07

I/06

I/05

I/04

I/03

Vss

I/02

I/01

I/00

A10

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

TSOP

VSOP

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