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28C64AT-20I/L

Description
3.3V Transceiver with Two EIA TIA 562 Receivers Active in Shutdown
Categorystorage    storage   
File Size125KB,10 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Download Datasheet Parametric View All

28C64AT-20I/L Overview

3.3V Transceiver with Two EIA TIA 562 Receivers Active in Shutdown

28C64AT-20I/L Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Parts packaging codeQFJ
package instructionQCCJ, LDCC32,.5X.6
Contacts32
Reach Compliance Code_compli
ECCN codeEAR99
Maximum access time200 ns
Other featuresAUTOMATIC WRITE; BULK ERASE; DATA RETENTION > 10 YEARS
command user interfaceNO
Data pollingYES
Data retention time - minimum10
JESD-30 codeR-PQCC-J32
JESD-609 codee0
length13.97 mm
memory density65536 bi
Memory IC TypeEEPROM
memory width8
Number of functions1
Number of terminals32
word count8192 words
character code8000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize8KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC32,.5X.6
Package shapeRECTANGULAR
Package formCHIP CARRIER
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Programming voltage5 V
Certification statusNot Qualified
ready/busyYES
Maximum seat height3.56 mm
Maximum standby current0.0001 A
Maximum slew rate0.03 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
switch bitNO
width11.43 mm
Maximum write cycle time (tWC)1 ms
Base Number Matches1
Obsolete Device
28C64A
64K (8K x 8) CMOS EEPROM
FEATURES
• Fast Read Access Time—150 ns
• CMOS Technology for Low Power Dissipation
- 30 mA Active
- 100
µA
Standby
• Fast Byte Write Time—200
µs
or 1 ms
• Data Retention >200 years
• High Endurance - Minimum 100,000 Erase/Write
Cycles
• Automatic Write Operation
- Internal Control Timer
- Auto-Clear Before Write Operation
- On-Chip Address and Data Latches
• Data Polling
• Ready/Busy
• Chip Clear Operation
• Enhanced Data Protection
- V
CC
Detector
- Pulse Filter
- Write Inhibit
• Electronic Signature for Device Identification
• 5-Volt-Only Operation
• Organized 8Kx8 JEDEC Standard Pinout
- 28-pin Dual-In-Line Package
- 32-pin PLCC Package
- 28-pin SOIC Package
• Available for Extended Temperature Ranges:
- Commercial: 0°C to +70°C
- Industrial:
-40°C to +85°C
PACKAGE TYPES
RDY/BSY
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
•1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
WE
NC
A8
A6
5
A9
A5
6
A11 A4
7
A3
8
OE
A10 A2
9
A1
10
CE
A0
11
I/O7
NC
12
I/O6
I/O0
13
I/O5
I/O4
I/O3
2
RDY/BSY
1
NU
4
A7
3
A12
32
Vcc
31
WE
18
19
30
NC
29
A8
28
A9
27
A11
26
NC
25
OE
24
A10
23
CE
22
I/O7
21
I/O6
14
15
16
17
• Pin 1 indicator on PLCC on top of package
BLOCK DIAGRAM
I/O0
I/O7
V
SS
V
CC
CE
OE
WE
Rdy/
Busy
Data Protection
Circuitry
Chip Enable/
Output Enable
Control Logic
Auto Erase/Write
Timing
Data
Poll
Program Voltage
Generation
A0
L
a
t
c
h
e
s
A12
Y
Decoder
X
Decoder
DESCRIPTION
The Microchip Technology Inc. 28C64A is a CMOS 64K non-
volatile electrically Erasable PROM. The 28C64A is
accessed like a static RAM for the read or write cycles with-
out the need of external components. During a “byte write”,
the address and data are latched internally, freeing the micro-
processor address and data bus for other operations. Fol-
lowing the initiation of write cycle, the device will go to a busy
state and automatically clear and write the latched data using
an internal control timer. To determine when the write cycle
is complete, the user has a choice of monitoring the Ready/
Busy output or using Data polling. The Ready/Busy pin is an
open drain output, which allows easy configuration in wired-
or systems. Alternatively, Data polling allows the user to read
the location last written to when the write operation is com-
plete. CMOS design and processing enables this part to be
used in systems where reduced power consumption and reli-
ability are required. A complete family of packages is offered
to provide the utmost flexibility in applications.
2004 Microchip Technology Inc.
I/O1
I/O2
Vss
NU
I/O3
I/O4
I/O5
Input/Output
Buffers
Y Gating
16K bit
Cell Matrix
DS11109K-page 1
20
DIP/SOIC
PLCC

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