28C64AFT-15I/SO datasheet, PDF

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28C64AFT-15I/SO: Description3.3V Transceiver with Two EIA TIA 562 Receivers Active in Shutdown; Categorystorage storage; File Size125KB，10 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

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28C64AFT-15I/SO Overview

3.3V Transceiver with Two EIA TIA 562 Receivers Active in Shutdown

28C64AFT-15I/SO Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	SOIC
package instruction	SOP, SOP28,.4
Contacts	28
Reach Compliance Code	_compli
ECCN code	EAR99
Maximum access time	150 ns
Other features	AUTOMATIC WRITE; BULK ERASE; DATA RETENTION > 10 YEARS
command user interface	NO
Data polling	YES
Data retention time - minimum	10
JESD-30 code	R-PDSO-G28
JESD-609 code	e0
memory density	65536 bi
Memory IC Type	EEPROM
memory width	8
Number of functions	1
Number of terminals	28
word count	8192 words
character code	8000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	8KX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP28,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Programming voltage	5 V
Certification status	Not Qualified
ready/busy	YES
Maximum standby current	0.0001 A
Maximum slew rate	0.03 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
switch bit	NO
Maximum write cycle time (tWC)	0.2 ms
Base Number Matches	1

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Obsolete Device

28C64A

64K (8K x 8) CMOS EEPROM

FEATURES

• Fast Read Access Time—150 ns

• CMOS Technology for Low Power Dissipation

- 30 mA Active

- 100

µA

Standby

• Fast Byte Write Time—200

µs

or 1 ms

• Data Retention >200 years

• High Endurance - Minimum 100,000 Erase/Write

Cycles

• Automatic Write Operation

- Internal Control Timer

- Auto-Clear Before Write Operation

- On-Chip Address and Data Latches

• Data Polling

• Ready/Busy

• Chip Clear Operation

• Enhanced Data Protection

- V

Detector

- Pulse Filter

- Write Inhibit

• Electronic Signature for Device Identification

• 5-Volt-Only Operation

• Organized 8Kx8 JEDEC Standard Pinout

- 28-pin Dual-In-Line Package

- 32-pin PLCC Package

- 28-pin SOIC Package

• Available for Extended Temperature Ranges:

- Commercial: 0°C to +70°C

- Industrial:

-40°C to +85°C

PACKAGE TYPES

RDY/BSY

A12

I/O0

I/O1

I/O2

•1

Vcc

A11 A4

A10 A2

I/O7

I/O6

I/O0

I/O5

I/O4

I/O3

RDY/BSY

A12

Vcc

A11

A10

I/O7

I/O6

• Pin 1 indicator on PLCC on top of package

BLOCK DIAGRAM

I/O0

I/O7

Rdy/

Busy

Data Protection

Circuitry

Chip Enable/

Output Enable

Control Logic

Auto Erase/Write

Timing

Data

Poll

Program Voltage

Generation

A12

Decoder

DESCRIPTION

The Microchip Technology Inc. 28C64A is a CMOS 64K non-

volatile electrically Erasable PROM. The 28C64A is

accessed like a static RAM for the read or write cycles with-

out the need of external components. During a “byte write”,

the address and data are latched internally, freeing the micro-

processor address and data bus for other operations. Fol-

lowing the initiation of write cycle, the device will go to a busy

state and automatically clear and write the latched data using

an internal control timer. To determine when the write cycle

is complete, the user has a choice of monitoring the Ready/

Busy output or using Data polling. The Ready/Busy pin is an

open drain output, which allows easy configuration in wired-

or systems. Alternatively, Data polling allows the user to read

the location last written to when the write operation is com-

plete. CMOS design and processing enables this part to be

used in systems where reduced power consumption and reli-

ability are required. A complete family of packages is offered

to provide the utmost flexibility in applications.



2004 Microchip Technology Inc.

I/O1

I/O2

Vss

I/O3

I/O4

I/O5

Input/Output

Buffers

Y Gating

16K bit

Cell Matrix

DS11109K-page 1

DIP/SOIC

PLCC

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