Obsolete Device
28C04A
4K (512 x 8) CMOS EEPROM
FEATURES
• Fast Read Access Time—150 ns
• CMOS Technology for Low Power Dissipation
- 30 mA Active
- 100
µA
Standby
• Fast Byte Write Time—200
µs
or 1 ms
• Data Retention >200 years
• Endurance - Minimum 10
4
Erase/Write Cycles
- Automatic Write Operation
- Internal Control Timer
- Auto-Clear Before Write Operation
- On-Chip Address and Data Latches
• Data Polling
• Chip Clear Operation
• Enhanced Data Protection
- V
CC
Detector
- Pulse Filter
- Write Inhibit
• 5-Volt-Only Operation
• Organized 512x8 JEDEC standard pinout
- 24-pin Dual-In-Line Package
- 32-pin PLCC Package
• Available for Extended Temperature Ranges:
- Commercial: 0°C to +70°C
- Industrial: -40°C to +85°C
PACKAGE TYPES
DIP
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
•1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Vcc
A8
NC
WE
OE
NC
CE
I/O7
I/O6
I/O5
I/O4
I/O3
32
Vcc
31
WE
18
19
28C04A
2
NC
1
NU
4
A7
3
NC
PLCC
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
5
6
7
8
9
10
11
12
13
30
NC
29
A8
28
NC
27
NC
26
NC
25
OE
24
NC
23
CE
22
I/O7
21
I/O6
20
28C04A
14
15
16
•
Pin 1 indicator on PLCC on top of package
BLOCK DIAGRAM
I/O0
I/O7
DESCRIPTION
The Microchip Technology Inc. 28C04A is a CMOS 4K
non-volatile electrically Erasable and Programmable
Read Only Memory (EEPROM). The 28C04A is
accessed like a static RAM for the read or write cycles
without the need of external components. During a
“byte write”, the address and data are latched inter-
nally, freeing the microprocessor address and data bus
for other operations. Following the initiation of write
cycle, the device will go to a busy state and automati-
cally clear and write the latched data using an internal
control timer. To determine when a write cycle is com-
plete, the 28C04A uses Data polling. Data polling
allows the user to read the location last written to when
the write operation is complete. CMOS design and pro-
cessing enables this part to be used in systems where
reduced power consumption and reliability are
required. A complete family of packages is offered to
provide the utmost flexibility in applications.
V
SS
V
CC
CE
OE
WE
Data Protection
Circuitry
Chip Enable/
Output Enable
Control Logic
Auto Erase/Write
Timing
I/O1
I/O2
Vss
NU
I/O3
I/O4
I/O5
17
Data
Poll
Input/Output
Buffers
Program Voltage
Generation
A0
L
a
t
c
h
e
s
A8
Y
Decoder
Y Gating
X
Decoder
4K bit
Cell Matrix
2004 Microchip Technology Inc.
DS11126H-page 1
28C04A
1.0
1.1
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS*
TABLE 1-1:
Name
A0 - A8
CE
OE
WE
I/O0 - I/O7
V
CC
V
SS
NC
NU
PIN FUNCTION TABLE
Function
Address Inputs
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
+5V Power Supply
Ground
No Connect; No Internal Connection
Not Used; No External Connection is
Allowed
V
CC
and input voltages w.r.t. V
SS
....... -0.6V to + 6.25V
Voltage on OE w.r.t. V
SS
...................... -0.6V to +13.5V
Output Voltage w.r.t. V
SS
.................-0.6V to V
CC
+0.6V
Storage temperature ..........................-65°C to +125°C
Ambient temp. with power applied .......-50°C to +95°C
*Notice:
Stresses above those listed under “Maximum Ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operation listings of
this specification is not implied. Exposure to maximum rating con-
ditions for extended periods may affect device reliability.
TABLE 1-2:
READ/WRITE OPERATION DC CHARACTERISTICS
V
CC
= +5V
±10%
Commercial (C): Tamb =
Industrial
(I): Tamb =
0°C to +70°C
-40°C to +85°C
Conditions
Parameter
Input Voltages
Input Leakage
Input Capacitance
Output Voltages
Output Leakage
Output Capacitance
Power Supply Current, Active
Power Supply Current, Standby
Status
Logic ‘1’
Logic ‘0’
Symbol
V
IH
V
IL
I
LI
C
IN
Min
2.0
-0.1
-10
Max
V
CC
+1
0.8
10
10
Units
V
V
µA
pF
V
V
µA
pF
mA
mA
mA
µA
V
IN
= -0.1V to V
CC
+1
V
IN
= 0V; Tamb = 25°C;
f = 1 MHz
I
OH
= -400
µA
I
OL
= 2.1 mA
V
OUT
= -0.1V
TO
V
CC
+ 0.1V
V
IN
= 0V; T
AMB
= 25°C;
f = 1 MHz
f = 5 MHz (Note 1)
V
CC
= 5.5V
CE = V
IH
(0°C to +70°C)
CE = V
IH
(-40°C to +85°C)
CE = V
CC
-0.3 to V
CC
+1
OE = V
CC
All inputs equal V
CC
or V
SS
Logic ‘1’
Logic ‘0’
V
OH
V
OL
I
LO
C
OUT
2.4
0.45
-10
10
12
30
2
3
100
TTL input
I
CC
TTL input
I
CC
(
S
)
TTL
I
CC
(
S
)
TTL
TTL input
CMOS input I
CC
(
S
)
CMOS
Note 1: AC power supply current above 5 MHz; 1 mA/MHz.
DS11126H-page 2
2004 Microchip Technology Inc.
28C04A
TABLE 1-3:
READ OPERATION AC CHARACTERISTICS
AC Testing Waveform:
Output Load:
Input Rise and Fall Times:
Ambient Temperature:
28C04A-15
Parameter
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE to OE High Output Float
Output Hold from Address, CE
or OE, whichever occurs first
Endurance
Sym
Min
t
ACC
t
CE
t
OE
t
OFF
t
OH
—
0
0
1M
—
Max
150
150
70
50
0
0
1M
—
Min
Max
200
200
80
55
0
0
1M
—
Min
Max
250
250
100
70
ns
ns
ns
ns
ns
cycles 25°C, Vcc =
5.0V, Block
Mode (Note)
OE = CE = V
IL
OE = V
IL
CE = V
IL
V
IH
= 2.4V; V
IL
= 0.45V; V
OH
= 2.0V; V
OL
= 0.8V
1 TTL Load + 100 pF
20 ns
Commercial (C): Tamb = 0°C to +70°C
Industrial
(I): Tamb = -40°C to +85°C
28C04A-20
28C04A-25
Units
Conditions
Note: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-1:
READ WAVEFORMS
2004 Microchip Technology Inc.
DS11126H-page 3
28C04A
TABLE 1-4:
BYTE WRITE AC CHARACTERISTICS
AC Testing Waveform:
Output Load:
Input Rise/Fall Times:
Ambient Temperature:
Parameter
Address Set-Up Time
Address Hold Time
Data Set-Up Time
Data Hold Time
Write Pulse Width
Write Pulse High Time
OE Hold Time
OE Set-Up Time
Data Valid Time
Write Cycle Time (28C04A)
Write Cycle Time (28C04AF)
Symbol
t
AS
t
AH
t
DS
t
DH
t
WPL
t
WPH
t
OEH
t
OES
t
DV
t
WC
t
WC
Min
10
50
50
10
100
50
10
10
1000
1
200
V
IH
= 2.4V; V
IL
= 0.45V; V
OH
= 2.0V; V
OL
= 0.8V
1 TTL Load + 100 pF
20 nsec
Commercial (C): Tamb= 0°C to 70°C
Industrial
(I): Tamb= -40°C to 85°C
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
Note 2
0.5 ms typical
100
µs
typical
Note 1
Remarks
Note 1: A write cycle can be initiated be CE or WE going low, whichever occurs last. The data is latched on the pos-
itive edge of CE or WE, whichever occurs first.
2: Data must be valid within 1000ns max. after a write cycle is initiated and must be stable at least until t
DH
after the positive edge of WE or CE, whichever occurs first.
FIGURE 1-2:
PROGRAMMING WAVEFORMS
V
IH
Address
V
IL
V
IH
CE, WE
V
IL
t
DV
Data In
V
IH
V
IL
t
OES
V
IH
OE
V
IL
t
OEH
t
DS
t
AS
t
AH
t
WPL
t
DH
DS11126H-page 4
2004 Microchip Technology Inc.
28C04A
FIGURE 1-3:
DATA POLLING WAVEFORMS
V
IH
Address
V
IL
Address Valid
t
ACC
t
CE
t
WPH
Last Written
Address Valid
V
IH
CE
V
IL
V
IH
WE
V
IL
t
WPL
t
OE
V
IH
OE
V
IL
t
DV
V
IH
Data
V
IL
Data In
Valid
t
WC
I/O7 Out
True Data Out
FIGURE 1-4:
CHIP CLEAR WAVEFORMS
V
IH
CE
V
IL
V
H
OE
V
IH
V
IH
WE
V
IL
t
W
= 10ms
t
S
= t
H
= 1µs
V
H
= 12.0V
±0.5V
t
S
t
W
t
H
2004 Microchip Technology Inc.
DS11126H-page 5
京公网安备 11010802033920号
EEWORLD
