591AD312M500DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> 591AD312M500DG

591AD312M500DG: DescriptionSINGLE FREQUENCY XO, OE PIN 1; CategoryPassive components; File Size416KB，16 Pages; ManufacturerSilicon Laboratories Inc

Download Datasheet Parametric View All

591AD312M500DG Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	591AD312M500DG	-	-	View	Buy Now

591AD312M500DG Overview

SINGLE FREQUENCY XO, OE PIN 1

591AD312M500DG Parametric

Parameter Name	Attribute value
type	XO (Standard)
frequency	312.5MHz
Function	enable/disable
output	LVPECL
Voltage - Power	3.3V
frequency stability	±7ppm
Absolute pulling range (APR)	-
Operating temperature	-40°C ~ 85°C
Current - Power (maximum)	125mA
grade	-
Installation type	surface mount
Package/casing	6-SMD, no leads
size/dimensions	0.276" long x 0.197" wide (7.00mm x 5.00mm)
Height - Installation (maximum)	0.071"（1.80mm）
Current - Power (disabled) (maximum)	75mA

Preview

Download Datasheet

View All

S i 5 9 0 / 5 91

1 ps M

I T T E R

RYSTAL

SC ILLA TOR

(XO)

(10 M H

Z TO

810 MH

)

Features

Available with any-frequency output



frequencies from 10 to 810 MHz



3rd generation DSPLL

with superior



jitter performance: 1 ps max jitter



Better frequency stability than SAW-



based oscillators



Internal fundamental mode crystal

ensures high reliability



Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry Standard 5x7 and

3.2x5 mm packages

Pb-free/RoHS-compliant

–40 to +85 ºC operating

temperature range

Si5602

Applications



Ordering Information:

See page 8.



SONET/SDH (OC-3/12/48)



Networking



SD/HD SDI/3G SDI video

Test and measurement



Storage



FPGA/ASIC clock generation

Description

The Si590/591 XO utilizes Silicon Laboratories’ advanced DSPLL

circuitry

to provide a low jitter clock at high frequencies. The Si590/591 supports any

frequency from 10 to 810 MHz. Unlike a traditional XO, where a unique

crystal is required for each output frequency, the Si590/591 uses one fixed

crystal to provide a wide range of output frequencies. This IC based

approach allows the crystal resonator to provide exceptional frequency

stability and reliability. In addition, DSPLL clock synthesis provides superior

supply noise rejection, simplifying the task of generating low jitter clocks in

noisy environments typically found in communication systems. The

Si590/591 IC based XO is factory configurable for a wide variety of user

specifications including frequency, supply voltage, output format, and

stability. Specific configurations are factory programmed at time of shipment,

thereby eliminating long lead times associated with custom oscillators.

Pin Assignments:

See page 7.

(Top View)

CLK–

GND

CLK+

Si590 (LVDS/LVPECL/CML)

Functional Block Diagram

CLK– CLK+

GND

CLK

17 k



Any-rate

10–810 MHz

DSPLL

Clock

Synthesis

Si590 (CMOS)

Fixed

Frequency

CLK–

17 k



GND

CLK+

GND

*Note: Output Enable High/Low Options Available – See Ordering Information

Si591 (LVDS/LVPECL/CML)

Rev. 1.2 6/18

Si590/591

Recommended Resources

Output voltage expansion circuit a

Radio double-tuned IF amplifier circuit

Simple integrated circuit quick tester circuit

Differential Input FET Buffered Current Source Circuit Diagram

Bi-stabilized power supply with fine adjustment composed of LM109 and LM120

ML-01G type automatic music flag raising ceremony dedicated integrated circuit

How much time difference can there be in running a statement like this in C language?: d=1024*cos(asin(a/1024))；...; smartygt Analog electronics

Bug in forum posting from normal mode to advanced mode?: Today I was going to post the first debugging of LPC4357 development, but I just wrote some words in the normal posting mode, and then I wanted to upload pictures, but I found that pictures could not ...; ou513 MCU

About the new BSP: Now I have a SMDK2442 development board and BSP, everything works fine; I made a new development board, also using 2442, for example, let's call it MV2442, I want to create a new BSP, but I don't want...; ywlgjy Embedded System

Invalid ROM Table appears when downloading from STlink: I made a STMF407 board myself. The downloading process was fine at first, but after downloading a few times, an InValid ROM Table error will appear. Does anyone know what the reason is?...; FireLife stm32/stm8

Looking for a proteus simulation component library containing energy metering chip components: I can't find the power chip in my component library, and I don't know how to make it myself, so I have to come here to ask for the finished product. As long as the component library has one of ADE7755...; baimua MCU

Summary of Python file operation methods: [i=s]This post was last edited by clinken on 2018-2-27 21:09[/i] [p=26, null, left][color=rgb(51, 51, 51)][font=-apple-system, BlinkMacSystemFont, "]The open function is indispensable for file operati...; clinken MicroPython Open Source section

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components