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PHB21N06LT,118

Description
MOSFET N-CH 55V 19A D2PAK
CategoryDiscrete semiconductor    The transistor   
File Size227KB,12 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
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PHB21N06LT,118 Overview

MOSFET N-CH 55V 19A D2PAK

PHB21N06LT,118 Parametric

Parameter NameAttribute value
Brand NameNexperia
MakerNexperia
Parts packaging codeD2PAK
package instructionSMALL OUTLINE, R-PSSO-G2
Contacts3
Manufacturer packaging codeSOT404
Reach Compliance Codenot_compliant
ECCN codeEAR99
Samacsys DescriptionMOSFET TAPE13 PWR-MOS
Other featuresLOGIC LEVEL COMPATIBLE
Avalanche Energy Efficiency Rating (Eas)34 mJ
Shell connectionDRAIN
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage55 V
Maximum drain current (ID)19 A
Maximum drain-source on-resistance0.075 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
JESD-30 codeR-PSSO-G2
JESD-609 codee3
Humidity sensitivity level1
Number of components1
Number of terminals2
Operating modeENHANCEMENT MODE
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Polarity/channel typeN-CHANNEL
Maximum pulsed drain current (IDM)76 A
surface mountYES
Terminal surfaceTin (Sn)
Terminal formGULL WING
Terminal locationSINGLE
transistor applicationsSWITCHING
Transistor component materialsSILICON
Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
tradename
Nexperia.
Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
application markets
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use
the references to Nexperia, as shown below.
Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,
use
http://www.nexperia.com
Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use
salesaddresses@nexperia.com
(email)
Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
the version, as shown below:
- © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
reserved
Should be replaced with:
-
© Nexperia B.V. (year). All rights reserved.
If you have any questions related to the data sheet, please contact our nearest sales office via e-mail
or telephone (details via
salesaddresses@nexperia.com).
Thank you for your cooperation and
understanding,
Kind regards,
Team Nexperia

PHB21N06LT,118 Related Products

PHB21N06LT,118 PHD21N06LT,118 PHP21N06LT,127
Description MOSFET N-CH 55V 19A D2PAK N-channel TrenchMOS logic level FET DPAK 3-Pin N-channel TrenchMOS logic level FET TO-220 3-Pin
Brand Name Nexperia Nexperia Nexperia
Parts packaging code D2PAK DPAK TO-220
package instruction SMALL OUTLINE, R-PSSO-G2 DPAK-3 PLASTIC, TO-220AB, 3 PIN
Contacts 3 3 3
Manufacturer packaging code SOT404 SOT428 SOT78
Reach Compliance Code not_compliant not_compliant compliant
ECCN code EAR99 EAR99 EAR99
Other features LOGIC LEVEL COMPATIBLE LOGIC LEVEL COMPATIBLE LOGIC LEVEL COMPATIBLE, FAST SWITCHING
Avalanche Energy Efficiency Rating (Eas) 34 mJ 34 mJ 34 mJ
Shell connection DRAIN DRAIN DRAIN
Configuration SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage 55 V 55 V 55 V
Maximum drain current (ID) 19 A 19 A 19 A
Maximum drain-source on-resistance 0.075 Ω 0.075 Ω 0.075 Ω
FET technology METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR
JESD-30 code R-PSSO-G2 R-PSSO-G2 R-PSFM-T3
Number of components 1 1 1
Number of terminals 2 2 3
Operating mode ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
Package shape RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE FLANGE MOUNT
Polarity/channel type N-CHANNEL N-CHANNEL N-CHANNEL
Maximum pulsed drain current (IDM) 76 A 76 A 76 A
surface mount YES YES NO
Terminal form GULL WING GULL WING THROUGH-HOLE
Terminal location SINGLE SINGLE SINGLE
transistor applications SWITCHING SWITCHING SWITCHING
Transistor component materials SILICON SILICON SILICON
JESD-609 code e3 - e3
Terminal surface Tin (Sn) - Matte Tin (Sn)
Peak Reflow Temperature (Celsius) - NOT SPECIFIED NOT SPECIFIED
Maximum time at peak reflow temperature - NOT SPECIFIED NOT SPECIFIED
Base Number Matches - 1 1
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