PSMN2R0-25MLD
8 April 2016
N-channel 25 V, 2.1 mΩ logic level MOSFET in LFPAK33
using NextPowerS3 Technology
Product data sheet
1. General description
Logic level gate drive N-channel enhancement mode MOSFET in LFPAK33 package.
NextPowerS3 portfolio utilising Nexperia’s unique “SchottkyPlus” technology delivers
high efficiency, low spiking performance usually associated with MOSFETS with an
integrated Schottky or Schottky-like diode but without problematic high leakage current.
NextPowerS3 is particularly suited to high efficiency applications at high switching
frequencies.
2. Features and benefits
•
•
•
•
•
•
•
•
Ultra low Q
G
, Q
GD
and Q
OSS
for high system efficiency, especially at higher switching
frequencies
Superfast switching with soft-recovery; s-factor > 1
Low spiking and ringing for low EMI designs
Unique “SchottkyPlus” technology; Schottky-like performance with < 1 µA leakage at
25 °C
Optimised for 4.5 V gate drive
Low parasitic inductance and resistance
High reliability clip bonded and solder die attach Mini Power SO8 package; no glue,
no wire bonds, qualified to 175 °C
Exposed leads for optimal visual solder inspection
3. Applications
•
•
•
•
•
•
On-board DC:DC solutions for server and telecommunications
Secondary-side synchronous rectification in telecommunication applications
Voltage regulator modules (VRM)
Point-of-Load (POL) modules
Power delivery for V-core, ASIC, DDR, GPU, VGA and system components
Brushed and brushless motor control
4. Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
Conditions
25 °C ≤ T
j
≤ 175 °C
V
GS
= 10 V; T
mb
= 25 °C;
Fig. 2
T
mb
= 25 °C;
Fig. 1
Min
-
-
-
Typ
-
-
-
Max
25
70
74
Unit
V
A
W
Nexperia
PSMN2R0-25MLD
N-channel 25 V, 2.1 mΩ logic level MOSFET in LFPAK33 using
NextPowerS3 Technology
Symbol
T
j
R
DSon
Parameter
junction temperature
Conditions
Min
-55
Typ
-
Max
175
Unit
°C
Static characteristics
drain-source on-state
resistance
V
GS
= 4.5 V; I
D
= 25 A; T
j
= 25 °C;
Fig. 10
V
GS
= 10 V; I
D
= 25 A; T
j
= 25 °C;
Fig. 10
Dynamic characteristics
Q
G(tot)
total gate charge
I
D
= 25 A; V
DS
= 12 V; V
GS
= 10 V;
Fig. 12; Fig. 13
I
D
= 25 A; V
DS
= 12 V; V
GS
= 4.5 V;
Fig. 12; Fig. 13
I
D
= 0 A; V
DS
= 0 V; V
GS
= 10 V
Q
GD
gate-drain charge
I
D
= 25 A; V
DS
= 12 V; V
GS
= 4.5 V;
Fig. 12; Fig. 13
Source-drain diode
S
softness factor
I
S
= 25 A; dI
S
/dt = -100 A/µs; V
GS
= 0 V;
V
DS
= 12 V;
Fig. 16
-
0.9
-
-
-
18.9
3.8
-
-
nC
nC
-
15.9
-
nC
-
34.4
-
nC
-
1.86
2.27
mΩ
-
2.5
3.06
mΩ
5. Pinning information
Table 2.
Pin
1
2
3
4
mb
Pinning information
Symbol Description
S
S
S
G
D
source
source
source
gate
mounting base; connected to
drain
1
2
3
4
Simplified outline
Graphic symbol
D
G
mbb076
S
LFPAK33 (SOT1210)
6. Ordering information
Table 3.
Ordering information
Package
Name
PSMN2R0-25MLD
LFPAK33
Description
Plastic single ended surface mounted package
(LFPAK33); 8 leads
Version
SOT1210
Type number
PSMN2R0-25MLD
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
8 April 2016
2 / 13
Nexperia
PSMN2R0-25MLD
N-channel 25 V, 2.1 mΩ logic level MOSFET in LFPAK33 using
NextPowerS3 Technology
7. Marking
Table 4.
Marking codes
Marking code
2D025L
Type number
PSMN2R0-25MLD
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
DGR
V
GS
P
tot
I
D
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
total power dissipation
drain current
T
mb
= 25 °C;
Fig. 1
V
GS
= 10 V; T
mb
= 25 °C;
Fig. 2
V
GS
= 10 V; T
mb
= 100 °C;
Fig. 2
I
DM
T
stg
T
j
T
sld(M)
V
ESD
I
S
I
SM
E
DS(AL)S
peak drain current
storage temperature
junction temperature
peak soldering temperature
electrostatic discharge voltage
HBM
pulsed; t
p
≤ 10 µs; T
mb
= 25 °C;
Fig. 3
Conditions
25 °C ≤ T
j
≤ 175 °C
25 °C ≤ T
j
≤ 175 °C; R
GS
= 20 kΩ
Min
-
-
-20
-
-
-
-
-55
-55
-
800
Max
25
25
20
74
70
70
555
175
175
260
-
Unit
V
V
V
W
A
A
A
°C
°C
°C
V
Source-drain diode
source current
peak source current
T
mb
= 25 °C
pulsed; t
p
≤ 10 µs; T
mb
= 25 °C
I
D
= 25 A; V
sup
≤ 25 V; R
GS
= 50 Ω;
V
GS
= 10 V; T
j(init)
= 25 °C; unclamped;
t
p
= 0.89 ms
[1]
Protected by 100% test
-
-
62
555
A
A
Avalanche ruggedness
non-repetitive drain-source
avalanche energy
[1]
-
361
mJ
PSMN2R0-25MLD
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
8 April 2016
3 / 13
Nexperia
PSMN2R0-25MLD
N-channel 25 V, 2.1 mΩ logic level MOSFET in LFPAK33 using
NextPowerS3 Technology
120
P
der
(%)
80
03aa16
I
D
(A)
125
150
aaa-021815
100
75
(1)
40
50
25
0
0
50
100
150
T
mb
(°C)
200
0
0
25
50
75
100
125
150 175
T
mb
(°C)
200
Fig. 1.
Normalized total power dissipation as a
function of mounting base temperature
Fig. 2.
V
GS
≥ 10 V
(1) Capped at 70A due to package
Continuous drain current as a function of
mounting base temperature
I
D
(A)
10
3
Limit R
DSon
= V
DS
/ I
D
10
2
t
p
= 10 us
100 us
aaa-021817
10
DC
1 ms
10 ms
100 ms
1
10
-1
10
-1
1
10
V
DS
(V)
10
2
T
mb
= 25 °C; I
DM
is a single pulse
Fig. 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
9. Thermal characteristics
Table 6.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
thermal resistance
from junction to
mounting base
Conditions
Fig. 4
Min
-
Typ
1.56
Max
2.02
Unit
K/W
PSMN2R0-25MLD
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
8 April 2016
4 / 13
Nexperia
PSMN2R0-25MLD
N-channel 25 V, 2.1 mΩ logic level MOSFET in LFPAK33 using
NextPowerS3 Technology
Symbol
R
th(j-a)
Parameter
thermal resistance
from junction to
ambient
Conditions
Fig. 5
Fig. 6
Min
-
-
Typ
57
178
Max
-
-
Unit
K/W
K/W
Z
th(j-mb)
(K/W)
10
aaa-021818
1 δ = 0.5
0.2
0.1
10
-1
0.05
0.02
single shot
10
-2
t
p
10
-3
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
P
δ=
t
p
T
t
T
t
p
(s)
1
Fig. 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
aaa-008476
aaa-008477
Fig. 5.
PCB layout for thermal resistance junction to
ambient 1" square pad; FR4 Board; 2oz copper
Fig. 6.
PCB layout for thermal resistance junction to
ambient minimum footprint; FR4 Board; 2oz
copper
10. Characteristics
Table 7.
Symbol
V
(BR)DSS
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
Conditions
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 1 mA; V
DS
=V
GS
; T
j
= 25 °C
Min
25
22.5
1.2
Typ
-
-
1.65
Max
-
-
2.2
Unit
V
V
V
Static characteristics
V
GS(th)
PSMN2R0-25MLD
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
8 April 2016
5 / 13
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