DATASHEET
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE
DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
Description
IDT's STAC9752/9753 are general purpose 20-bit, full
duplex, audio CODECs conforming to the analog
component specification of AC'97 (Audio CODEC 97
Component Specification Rev. 2.3). The STAC9752/9753
incorporate IDT's proprietary
Σ∆
technology to achieve a
DAC SNR in excess of 90dB. The DACs, ADCs and mixer
are integrated with analog I/Os, which include four analog
line-level stereo inputs, two analog line-level mono inputs,
two stereo outputs, and one mono output channel. The
STAC9752/9753 include digital output capability for support
of modern PC systems with an output that supports the
SPDIF format. The STAC9752/9753 are standard
2-channel stereo CODECs. With IDT’s headphone
capability, headphones can be driven without an external
amplifier. The STAC9752/9753 may be used as a
secondary or tertiary CODECs, with STAC9700/21/44/56/
08/84/50/66 as the primary, in a multiple CODEC
configuration conforming to the AC'97 Rev. 2.3
specification. This configuration can provide the true
six-channel, AC-3 playback required for DVD applications.
The STAC9752/9753 communicate via the five AC-Link
lines to any digital component of AC'97, providing flexibility
in the audio system design. Packaged in an AC'97
compliant 48-pin TQFP, the STAC9752/9753 can be placed
on the motherboard, daughter boards, PCI, AMR, CNR,
MDC or ACR cards.
STAC9752/9753
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5-wire AC-Link protocol compliance
20-bit SPDIF Output
Internal Jack Sensing on Headphone and Line_Out
Internal Microphone Input Sensing
Digital PC Beep Option
Extended AC’97 2.3 Paging Registers
Adjustable VREF amplifier
Digital-ready status
General purpose I/Os
Crystal Elimination Circuit
Headphone drive capability (50 mW)
0dB, 10dB, 20dB, and 30dB microphone boost
capability
+3.3 V (STAC9753) and +5 V (STAC9752) analog
power supply options
Pin compatible with the STAC9700, STAC9721,
STAC9756
100% pin compatible with STAC9750 and
STAC9766
IDT Surround (SS3D) Stereo Enhancement
Energy saving dynamic power modes
Multi-CODEC option (Intel AC'97 rev 2.3)
Six analog line-level inputs
90dB SNR Line to Line
SNR > 89dB through Mixer and DAC
Features
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High performance
Σ∆
technology
AC’97 Rev 2.3 compliant
20-bit full duplex stereo ADCs, DACs
Independent sample rates for ADCs & DACs
IDT™
1
STAC9752/9753
V 3.3 101006
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
TABLE OF CONTENTS
1. PRODUCT BRIEF ...................................................................................................................... 7
1.1. Description ........................................................................................................................................ 7
1.2. STAC9752/9753 Block Diagram ........................................................................................................ 8
1.3. Key Specifications ............................................................................................................................. 8
1.4. Related Materials .............................................................................................................................. 9
1.5. Additional Support ............................................................................................................................. 9
2. CHARACTERISTICS AND SPECIFICATIONS .......................................................................10
2.1. Electrical Specifications ................................................................................................................... 10
2.1.1. Absolute Maximum Ratings ............................................................................................... 10
2.1.2. Recommended Operation Conditions .............................................................................. 10
2.1.3. Power Consumption ......................................................................................................... 11
2.1.4. AC-Link Static Digital Specifications ................................................................................. 12
2.1.5. STAC9752 5 V Analog Performance Characteristics ....................................................... 12
2.1.6. STAC9753 3.3V Analog Performance Characteristics .....................................................14
2.2. AC Timing Characteristics ............................................................................................................... 16
2.2.1. Cold Reset ......................................................................................................................... 16
2.2.2. Warm Reset ....................................................................................................................... 16
2.2.3. Clocks ................................................................................................................................ 17
2.2.4. STAC9752/9753 Crystal Elimination Circuit and Clock Frequencies ................................17
2.2.5. Data Setup and Hold ........................................................................................................ 18
2.2.6. Signal Rise and Fall Times ............................................................................................... 18
2.2.7. AC-Link Low Power Mode Timing .................................................................................... 19
2.2.8. ATE Test Mode ................................................................................................................. 19
3. TYPICAL CONNECTION DIAGRAM .......................................................................................20
3.1. Slit Independent Power Supply Operation ...................................................................................... 21
4. CONTROLLER, CODEC AND AC-LINK .................................................................................23
4.1. AC-Link Physical Interface .............................................................................................................. 23
4.2. Controller to Single CODEC ............................................................................................................ 23
4.3. Controller to Multiple CODECs ........................................................................................................ 25
4.3.1. Primary CODEC Addressing ............................................................................................. 25
4.3.2. Secondary CODEC Addressing ........................................................................................ 25
4.3.3. CODEC ID Strapping ......................................................................................................... 26
4.4. Clocking for Multiple CODEC Implementations ............................................................................... 26
4.5. STAC9752/9753 as a Primary CODEC ........................................................................................... 26
4.5.1. STAC9752/9753 as a Secondary CODEC ........................................................................ 26
4.6. AC-Link Power Management ........................................................................................................... 27
4.6.1. Powering down the AC-Link .............................................................................................. 27
4.6.2. Waking up the AC-Link ...................................................................................................... 27
4.6.3. CODEC Reset ................................................................................................................... 28
5. AC-LINK DIGITAL INTERFACE ..............................................................................................29
5.1. Overview ......................................................................................................................................... 29
5.2. AC-Link Serial Interface Protocol .................................................................................................... 30
5.2.1. AC-Link Variable Sample Rate Operation ......................................................................... 30
5.2.2. Variable Sample Rate Signaling Protocol .......................................................................... 30
5.2.3. Primary and Secondary CODEC Register Addressing ...................................................... 32
5.3. AC-Link Output Frame (SDATA_OUT) ............................................................................................ 32
5.3.1. Slot 0: TAG / CODEC ID ................................................................................................... 34
5.3.2. Slot 1: Command Address Port ......................................................................................... 34
5.3.3. Slot 2: Command Data Port ............................................................................................... 35
5.3.4. Slot 3: PCM Playback Left Channel .................................................................................. 35
5.3.5. Slot 4: PCM Playback Right Channel ................................................................................ 35
5.3.6. Slot 5: Modem Line 1 Output Channel .............................................................................. 35
5.3.7. Slot 6 - 11: DAC ................................................................................................................. 35
IDT™
2
STAC9752/9753
REV 3.3 1206
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
5.3.8. Slot 12: Audio GPIO Control Channel ............................................................................... 36
5.4. AC-Link Input Frame (SDATA_IN) ................................................................................................. 36
5.4.1. Slot 0: TAG ........................................................................................................................37
5.4.2. Slot 1: Status Address Port / SLOTREQ signalling bits .....................................................37
5.4.3. Slot 2: Status Data Port ..................................................................................................... 38
5.4.4. Slot 3: PCM Record Left Channel ..................................................................................... 38
5.4.5. Slot 4: PCM Record Right Channel ................................................................................... 38
5.4.6. Slot 5: Modem Line 1 ADC ................................................................................................ 38
5.4.7. Slot 6 - 9: ADC ................................................................................................................... 38
5.4.8. Slots 7 & 8: Vendor Reserved ........................................................................................... 39
5.4.9. Slot 10 & 11: ADC ............................................................................................................. 39
5.4.10. Slot 12: Reserved ............................................................................................................ 39
5.5. AC-Link Interoperability Requirements and Recommendations ...................................................... 40
5.5.1. “Atomic slot” Treatment of Slot 1 Address and Slot 2 Data ...............................................40
5.6. Slot Assignments for Audio ............................................................................................................. 41
6. STAC9752/9753 MIXER ..........................................................................................................43
7. MIXER FUNCTIONAL DIAGRAMS ........................................................................................44
7.1. Analog Mixer Input ......................................................................................................................... 45
7.2. Mixer Analog Output ....................................................................................................................... 45
7.3. SPDIF Digital Mux ...........................................................................................................................45
7.4. PC Beep Implementation ................................................................................................................ 46
7.4.1. Analog PC Beep ................................................................................................................ 46
7.4.2. Digital PC Beep ................................................................................................................. 46
8. PROGRAMMING REGISTERS ...............................................................................................47
8.1. Register Descriptions ...................................................................................................................... 48
8.1.1. Reset (00h) ....................................................................................................................... 48
8.1.2. Master Volume Registers (02h) ........................................................................................ 48
8.1.3. Headphone Volume Registers (04h) ................................................................................. 49
8.1.4. Master Volume MONO (06h) ............................................................................................ 50
8.1.5. PC BEEP Volume (0Ah) ................................................................................................... 51
8.1.6. Phone Volume (Index 0Ch) .............................................................................................. 51
8.1.7. Mic Volume (Index 0Eh) .................................................................................................... 52
8.1.8. LineIn Volume (Index 10h) ............................................................................................... 52
8.1.9. CD Volume (Index 12h) .................................................................................................... 53
8.1.10. Video Volume (Index 14h) ............................................................................................. 53
8.1.11. Aux Volume (Index 16h) ................................................................................................. 54
8.1.12. PCMOut Volume (Index 18h) ......................................................................................... 54
8.1.13. Record Select (1Ah) ....................................................................................................... 55
8.1.14. Record Gain (1Ch) ......................................................................................................... 55
8.1.15. General Purpose (20h) ................................................................................................... 56
8.1.16. 3D Control (22h) ............................................................................................................. 56
8.1.17. Audio Interrupt and Paging (24h) .................................................................................... 57
8.1.18. Powerdown Ctrl/Stat (26h) .............................................................................................. 58
8.1.19. Extended Audio ID (28h) ................................................................................................ 59
8.1.20. Extended Audio Control/Status (2Ah) ............................................................................. 61
8.1.21. PCM DAC Rate Registers (2Ch and 32h) ...................................................................... 63
8.1.22. PCM DAC Rate (2Ch) .................................................................................................... 63
8.1.23. PCM LR ADC Rate (32h) ............................................................................................... 63
8.1.24. SPDIF Control (3Ah) ........................................................................................................ 64
8.2. General Purpose Input & Outputs ................................................................................................... 64
8.2.1. EAPD ................................................................................................................................. 64
8.2.2. GPIO Pin Definitions .......................................................................................................... 65
8.2.3. GPIO Pin Implementation .................................................................................................. 65
8.2.4. Extended Modem Status and Control Register (3Eh) ........................................................65
8.2.5. GPIO Pin Configuration Register (4Ch) ............................................................................. 66
IDT™
3
STAC9752/9753
REV 3.3 1206
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
8.2.6. GPIO Pin Polarity/Type Register (4Eh) ............................................................................. 66
8.2.7. GPIO Pin Sticky Register (50h) ......................................................................................... 66
8.2.8. GPIO Pin Mask Register (52h) .......................................................................................... 67
8.2.9. GPIO Pin Status Register (54h) ........................................................................................ 67
8.3. Extended CODEC Registers Page Structure Definition .................................................................. 68
8.3.1. Extended Registers Page 00 ............................................................................................. 68
8.3.2. Extended Registers Page 01 ............................................................................................. 68
8.3.3. Extended Registers Page 02, 03 ....................................................................................... 68
8.4. STAC9752/9753 Paging Registers ................................................................................................. 69
8.4.1. CODEC Class/Rev (60h
Page 01h
) ............................................................................... 69
8.4.2. PCI SVID (62h
Page 01h
) ............................................................................................... 70
8.4.3. PCI SSID (64h
Page 01h
) ............................................................................................... 70
8.4.4. Function Select (66h
Page 01h
) ...................................................................................... 71
8.4.5. Function Information (68h
Page 01h
) .............................................................................. 72
8.4.6. Digital Audio Control (6Ah, Page 00h) ............................................................................... 73
8.4.7. Sense Details (6Ah
Page 01h
) ........................................................................................ 74
8.4.8. Revision Code (6Ch) ........................................................................................................ 76
8.4.9. Analog Special (6Eh) ......................................................................................................... 76
8.4.10. Analog Current Adjust (72h) ............................................................................................ 77
8.4.11. EAPD Access Register (74h) .......................................................................................... 77
8.4.12. High Pass Filter Bypass (78h) ........................................................................................ 78
8.5. Vendor ID1 and ID2 (Index 7Ch and 7Eh) ...................................................................................... 79
8.5.1. Vendor ID1 (7Ch) ............................................................................................................. 79
8.5.2. Vendor ID2 (7Eh) ............................................................................................................... 79
9. LOW POWER MODES ...........................................................................................................80
10. MULTIPLE CODEC SUPPORT ............................................................................................82
10.1. Primary/Secondary CODEC Selection .......................................................................................... 82
10.1.1. Primary CODEC Operation ............................................................................................ 82
10.1.2. Secondary CODEC Operation ........................................................................................ 82
10.2. Secondary CODEC Register Access Definitions .......................................................................... 83
11. TESTABILITY ........................................................................................................................84
11.0.1. ATE Test Mode ................................................................................................................ 84
12. PIN DESCRIPTION ................................................................................................................85
12.1. Digital I/O ...................................................................................................................................... 86
12.2. Analog I/O .................................................................................................................................... 87
12.3. Filter/References .......................................................................................................................... 88
12.4. Power and Ground Signals .......................................................................................................... 88
13. ORDERING INFORMATION ..................................................................................................89
14. PACKAGE DRAWING ...........................................................................................................89
15. 48-PIN LQFP SOLDER REFLOW PROFILE .........................................................................90
15.1. Standard Reflow Profile Data ........................................................................................................ 90
15.2. Pb Free Process - Package Classification Reflow Temperatures ................................................. 91
16. APPENDIX A: PROGRAMMING REGISTERS .....................................................................92
17. REVISION HISTORY .............................................................................................................94
IDT™
4
STAC9752/9753
REV 3.3 1206
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
LIST OF FIGURES
Figure 1. Block Diagram ................................................................................................................................. 8
Figure 2. Cold Reset Timing ......................................................................................................................... 16
Figure 3. Warm Reset Timing ....................................................................................................................... 16
Figure 4. Clocks Timing ............................................................................................................................... 17
Figure 5. Data Setup and Hold Timing ......................................................................................................... 18
Figure 6. Signal Rise and Fall Times Timing ................................................................................................ 18
Figure 7. AC-Link Low Power Mode Timing
.............................................................................................. 19
Figure 8. ATE Test Mode Timing ............................................................................................................... 19
Figure 9. Typical Connection Diagram .......................................................................................................... 20
Figure 10. Split Independent Power Supply Operation ................................................................................. 22
Figure 11. AC-Link to its Companion Controller ........................................................................................... 23
Figure 12. CODEC Clock Source Detection .................................................................................................. 24
Figure 13. STAC9752/9753 Powerdown Timing .......................................................................................... 27
Figure 14. Bi-directional AC-Link Frame with Slot assignments ................................................................... 29
Figure 15. AC-Link Audio Output Frame ...................................................................................................... 33
Figure 16. Start of an Audio Output Frame ................................................................................................... 33
Figure 17. STAC9752/9753 Audio Input Frame ........................................................................................... 36
Figure 18. Start of an Audio Input Frame ...................................................................................................... 36
Figure 19. Bi-directional AC-Link Frame with Slot assignments ................................................................... 41
Figure 20. STAC9752 2-Channel Mixer Functional Diagram ........................................................................ 44
Figure 21. STAC9753 2-Channel Mixer Functional Diagram .......................................................................44
Figure 22. Example of STAC9752/9753 Powerdown/Powerup flow ...........................................................80
Figure 23. Powerdown/Powerup flow with analog still alive ......................................................................... 81
Figure 24. Pin Description Drawing ............................................................................................................... 85
Figure 25. Reflow Profile ..............................................................................................................................90
IDT™
5
STAC9752/9753
REV 3.3 1206
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
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