AT49SV163D-80TU datasheet, PDF

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AT49SV163D-80TU: DescriptionIC FLASH 16M PARALLEL 48TSOP; Categorystorage; File Size436KB，30 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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AT49SV163D-80TU Overview

IC FLASH 16M PARALLEL 48TSOP

AT49SV163D-80TU Parametric

Parameter Name	Attribute value
memory type	non-volatile
memory format	flash memory
technology	FLASH
storage	16Mb （1M x 16）
Write cycle time - words, pages	70ns
interview time	80ns
memory interface	in parallel
Voltage - Power	1.65 V ~ 1.95 V
Operating temperature	-40°C ~ 85°C（TC）
Installation type	surface mount
Package/casing	48-TFSOP (0.724", 18.40mm wide)
Supplier device packaging	48-TSOP

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Features

•

Single Voltage Read/Write Operation: 1.65V to 1.95V

•

Access Time – 80 ns

•

Sector Erase Architecture

– Thirty-one 32K Word (64K Bytes) Sectors with Individual Write Lockout

– Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout

Fast Word Program Time – 10 µs

Fast Sector Erase Time – 100 ms

Suspend/Resume Feature for Erase and Program

– Supports Reading and Programming from Any Sector by Suspending Erase

of a Different Sector

– Supports Reading Any Word in the Non-suspending Sectors by Suspending

Programming of Any Other Word

Low-power Operation

– 10 mA Active

– 15 µA Standby

Data Polling, Toggle Bit, Ready/Busy for End of Program Detection

VPP Pin for Write Protection and Accelerated Program Operation

RESET Input for Device Initialization

Sector Lockdown Support

TSOP and CBGA Package Options

Top or Bottom Boot Block Configuration Available

128-bit Protection Register

Minimum 100,000 Erase Cycles

Common Flash Interface (CFI)

•

16-megabit

(1M x 16)

1.8-volt Only

Flash Memory

AT49SV163D

AT49SV163DT

1. Description

The AT49SV163D(T) is a 1.8-volt 16-megabit Flash memory organized as 1,048,576

words of 16 bits each. The memory is divided into 39 sectors for erase operations.

The device is offered in a 48-lead TSOP and a 48-ball CBGA package. The device

has CE and OE control signals to avoid any bus contention. This device can be read

or reprogrammed using a single power supply, making it ideally suited for in-system

programming.

The device powers on in the read mode. Command sequences are used to place the

device in other operation modes such as program and erase. The device has the

capability to protect the data in any sector (see

“Sector Lockdown” on page 6).

To increase the flexibility of the device, it contains an Erase Suspend and Program

Suspend feature. This feature will put the erase or program on hold for any amount of

time and let the user read data from or program data to any of the remaining sectors

within the memory. The end of a program or an erase cycle is detected by the

READY/BUSY pin, Data Polling or by the toggle bit.

The VPP pin provides data protection. When the V

input is below 0.4V, the program

and erase functions are inhibited. When V

is at 1.65V or above, normal program

and erase operations can be performed. With V

at 10.0V, the program (Dual-word

Program command) operation is accelerated.

3656A–FLASH–2/07

4.2

Read

The AT49SV163D(T) is accessed like an EPROM. When CE and OE are low and WE is high,

the data stored at the memory location determined by the address pins are asserted on the

outputs. The outputs are put in the high impedance state whenever CE or OE is high. This

dual-line control gives designers flexibility in preventing bus contention.

4.3

Reset

A RESET input pin is provided to ease some system applications. When RESET is at a logic

high level, the device is in its standard operating mode. A low level on the RESET input halts

the present device operation and puts the outputs of the device in a high impedance state.

When a high level is reasserted on the RESET pin, the device returns to the read or standby

mode, depending upon the state of the control inputs.

4.4

Erase

Before a word can be reprogrammed, it must be erased. The erased state of memory bits is a

logical “1”. The entire device can be erased by using the Chip Erase command or individual

sectors can be erased by using the Sector Erase command.

4.4.1

Chip Erase

The entire device can be erased at one time by using the six-byte chip erase software code.

After the chip erase has been initiated, the device will internally time the erase operation so

that no external clocks are required. The maximum time to erase the chip is t

If the sector lockdown has been enabled, the chip erase will not erase the data in the sector

that has been locked out; it will erase only the unprotected sectors. After the chip erase, the

device will return to the read or standby mode.

4.4.2

Sector Erase

As an alternative to a full chip erase, the device is organized into 39 sectors (SA0 - SA38) that

can be individually erased. The Sector Erase command is a six-bus cycle operation. The sec-

tor address is latched on the falling WE edge of the sixth cycle while the 30H data input

command is latched on the rising edge of WE. The sector erase starts after the rising edge of

WE of the sixth cycle. The erase operation is internally controlled; it will automatically time to

completion. The maximum time to erase a sector is t

SEC

. When the sector programming lock-

down feature is not enabled, the sector will erase (from the same Sector Erase command). An

attempt to erase a sector that has been protected will result in the operation terminating

immediately.

4.5

Word Programming

Once a memory block is erased, it is programmed (to a logical “0”) on a word-by-word basis.

Programming is accomplished via the internal device command register and is a four-bus

cycle operation. The device will automatically generate the required internal program pulses.

Any commands written to the chip during the embedded programming cycle will be ignored. If

a hardware reset happens during programming, the data at the location being programmed

will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase

operations can convert “0”s to “1”s. Programming is completed after the specified t

cycle

time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a

program cycle. If the erase/program status bit is a “1”, the device was not able to verify that the

erase or program operation was performed successfully.

AT49SV163D(T)

3656A–FLASH–2/07

AT49SV163D(T)

4.6

VPP Pin

The circuitry of the AT49SV163D(T) is designed so that the device cannot be programmed or

erased if the V

voltage is less that 0.4V. When V

is at 1.65V or above, normal program

and erase operations can be performed. The VPP pin cannot be left floating.

4.7

Program/Erase Status

The device provides several bits to determine the status of a program or erase operation: I/O2,

I/O3, I/O5, I/O6 and I/O7. The

“Status Bit Table” on page 11

and the following four sections

describe the function of these bits. To provide greater flexibility for system designers, the

AT49SV163D(T) contains a programmable configuration register. The configuration register

allows the user to specify the status bit operation. The configuration register can be set to one

of two different values, “00” or “01”. If the configuration register is set to “00”, the part will auto-

matically return to the read mode after a successful program or erase operation. If the

configuration register is set to a “01”, a Product ID Exit command must be given after a suc-

cessful program or erase operation before the part will return to the read mode. It is important

to note that whether the configuration register is set to a “00” or to a “01”, any unsuccessful

program or erase operation requires using the Product ID Exit command to return the device

to read mode. The default value (after power-up) for the configuration register is “00”. Using

the four-bus cycle Set Configuration Register command as shown in the

“Command Definition

Table” on page 12,

the value of the configuration register can be changed. Voltages applied to

the RESET pin will not alter the value of the configuration register. The value of the configura-

tion register will affect the operation of the I/O7 status bit as described below.

4.7.1

Data Polling

The AT49SV163D(T) features Data Polling to indicate the end of a program cycle. If the status

configuration register is set to a “00”, during a program cycle an attempted read of the last

word loaded will result in the complement of the loaded data on I/O7. Once the program cycle

has been completed, true data is valid on all outputs and the next cycle may begin. During a

chip or sector erase operation, an attempt to read the device will give a “0” on I/O7. Once the

program or erase cycle has completed, true data will be read from the device. Data Polling

may begin at any time during the program cycle. Please see

“Status Bit Table” on page 11

for

more details.

If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while the

device is actively programming or erasing data. I/O7 will go high when the device has com-

pleted a program or erase operation. Once I/O7 has gone high, status information on the other

pins can be checked.

The Data Polling status bit must be used in conjunction with the erase/program and V

status

bit as shown in the algorithm in

Figures 4-1 and 4-2

page 9.

4.7.2

Toggle Bit

In addition to Data Polling the AT49SV163D(T) provides another method for determining the

end of a program or erase cycle. During a program or erase operation, successive attempts to

read data from the memory will result in I/O6 toggling between one and zero. Once the pro-

gram cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the

toggle bit may begin at any time during a program cycle. Please see

“Status Bit Table” on

page 11

for more details.

The toggle bit status bit should be used in conjunction with the erase/program and V

status

bit as shown in the algorithm in

Figures 4-3 and 4-3

page 10.

3656A–FLASH–2/07

AT49SV163D-80TU Related Products

	AT49SV163D-80TU	AT49SV163D-80CU	AT49SV163DT-80TU
Description	IC FLASH 16M PARALLEL 48TSOP	IC FLASH 16M PARALLEL 48CBGA	IC FLASH 16M PARALLEL 48TSOP
memory type	non-volatile	non-volatile	non-volatile
memory format	flash memory	flash memory	flash memory
technology	FLASH	FLASH	FLASH
storage	16Mb （1M x 16）	16Mb （1M x 16）	16Mb （1M x 16）
Write cycle time - words, pages	70ns	70ns	70ns
interview time	80ns	80ns	80ns
memory interface	in parallel	in parallel	in parallel
Voltage - Power	1.65 V ~ 1.95 V	1.65 V ~ 1.95 V	1.65 V ~ 1.95 V
Operating temperature	-40°C ~ 85°C（TC）	-40°C ~ 85°C（TC）	-40°C ~ 85°C（TC）
Installation type	surface mount	surface mount	surface mount
Package/casing	48-TFSOP (0.724", 18.40mm wide)	48-CBGA	48-TFSOP (0.724", 18.40mm wide)
Supplier device packaging	48-TSOP	48-CBGA（7x10）	48-TSOP

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