PCA9525DP,118 datasheet, PDF - EEWORLD Datasheet

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PCA9525DP,118: DescriptionIC REDRIVER I2C 1CH 8TSSOP; CategoryAnalog mixed-signal IC Drivers and interfaces; File Size210KB，22 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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PCA9525DP,118 Overview

IC REDRIVER I2C 1CH 8TSSOP

PCA9525DP,118 Parametric

Parameter Name	Attribute value
Source Url Status Check Date	2013-06-14 00:00:00
Brand Name	NXP Semiconductor
Is it Rohs certified?	conform to
parentfamilyid	4095387
Maker	NXP
Parts packaging code	TSSOP
Contacts	8
Manufacturer packaging code	SOT505-1
Reach Compliance Code	compliant
compound_id	4099390

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PCA9525

Simple 2-wire bus buffer

Rev. 1 — 25 February 2011

Product data sheet

1. General description

The PCA9525 is a monolithic CMOS integrated circuit for bus buffering in applications

including I

C-bus, SMBus, DDC, PMBus, and other systems based on similar principles.

The buffer extends the bus load limit by buffering both the SCL and SDA lines, allowing

the maximum permissible bus capacitance on both sides of the buffer.

The PCA9525 includes a unidirectional buffer for the clock signal, and a bidirectional

buffer for the data signal. Slave devices which employ clock stretching are therefore not

supported.

In its most basic implementation, the buffer will allow an extended number of slave

devices to be attached to one (or more) master devices. In this case, all master devices

would be positioned on the Sxx_IN side of the PCA9525.

The direction pin (DIR) further enhances this function by allowing the unidirectional clock

signal to be reversed, thus allowing master devices on both sides of the buffer.

The enable (EN) function allows sections of the bus to be isolated. Individual parts of the

system can be brought on-line successively. This means a controlled start-up using a

diverse range of components, operating speeds and loads is easily achieved.

2. Features and benefits

Simple impedance isolating buffer for 2-wire buses

4 mA maximum static open-drain pull-down capability supports a wide range of bus

standards

Works with I

C-bus (Standard-mode, Fast-mode), SMBus (standard and high power

mode), and PMBus

Fast switching times allow operation in excess of 1 MHz

Enable allows bus segments to be disconnected

Hysteresis on inputs provides noise immunity

Operating voltages from 2.7 V to 5.5 V

Very low supply current

Uncomplicated characteristics suitable for quick implementation in most common

2-wire bus applications

NXP Semiconductors

PCA9525

Simple 2-wire bus buffer

clocking when communicating with them. The buffer includes hysteresis to ensure clean

switching signals are output, especially with slow rise times on high capacitively loaded

buses. Output ports are open-drain type and require external pull-up resistors.

7.3 SDA_IN, SDA_OUT — data signal inputs/outputs

The data signal buffer is bidirectional. The port (SDA_IN, SDA_OUT) which first falls

below the ‘lock voltage’ V

lock

, will take control of the buffer direction and ‘lock out’ signals

coming from the opposite side. As the ‘input’ signal continues to fall, it will then drive the

‘output’ side LOW. Again, hysteresis is applied to the buffer to minimize the effects of

noise.

At some points during the communication, the data direction will reverse, e.g., when the

slave transmits an acknowledge (ACK), or responds with its register contents. During

these times, the controlling ‘input’ side will have to rise back above the unlock voltage

unlock

) before it releases the ‘lock’, which then allows the ‘output’ side to gain control,

and pull (what was) the ‘input’ side LOW again. This will cause a ‘pulse’ on the ‘input’ side,

which can be quite a long duration in high capacitance buses. However, this pulse will not

interfere with the actual data transmission, as it should not occur during times of clock line

transition (during normal I

C-bus and SMBus protocols), and thus data signal set-up time

requirements are still met. Ports are open-drain type and require external pull-up resistors.

7.4 Enable (EN) — activate buffer operations

The active HIGH enable input (EN) can be used to disable the buffer, for the purpose of

isolating sections of the bus. The IC should only be disabled when the bus is idle. This

prevents truncation of commands which may confuse other devices on the bus. Enable

(EN) may also be used to progressively activate sections of the bus during system

start-up. Bus sections slow to respond on power-up can be kept isolated from the main

system to avoid interference and collisions. The pin must be externally driven to a valid

state.

7.5 Direction (DIR) — clock buffer direction control

The direction input (DIR) is used to change the signal direction of the SCL ports. When the

DIR pin is logic LOW, the clock signal input is SCL_IN and the buffered output is

SCL_OUT. When the DIR pin is logic HIGH, the clock signal input is SCL_OUT and the

buffered output is SCL_IN. The pin must be externally driven to a valid state.

PCA9525

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 25 February 2011

4 of 22

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