PCA9621
65 mA 8-bit 2-wire bus output port
Rev. 1 — 9 March 2011
Product data sheet
1. General description
The PCA9621 is a monolithic CMOS integrated circuit for general purpose output drive
configurable from a 2-wire bus interface (including I
2
C-bus, SMBus, PMBus, and other
systems based on similar principles). Output ports have a 65 mA sink capability, making
them ideal for driving LEDs.
The state of the outputs is determined by a programmable 8-bit register which can be read
and written via signals from the 2-wire bus (e.g., I
2
C-bus or similar).
The 2-wire bus interface also has 30 mA Fast-mode Plus (Fm+) capability, and
consequently can be run in excess of 1 MHz or up to 4000 pF capacitance. As such, the
PCA9621 can be connected to other 2-wire devices across long cable connections.
It can be mixed with other Fast-mode Plus slaves in systems driven by Fm+ buffers or by
the PCA9646 (fully buffered 4-channel bus switch) to build large scale systems with
high-speed or high-capacitance drive capability, for example large scale LED displays or
controlled lighting.
2. Features and benefits
8 individually selectable open-drain output ports
65 mA static sink capability on all output ports
Ports may be paralleled for up to 500 mA drive
Ideal for simple LED or general purpose output drive
Fast-mode Plus (30 mA, 4000 pF) 2-wire bus capability
Works with I
2
C-bus (Standard-mode, Fast-mode, and Fast-mode Plus), SMBus
(standard and high power mode), and PMBus
Fast switching times allow operation in excess of 1 MHz
Operating voltages from 2.7 V to 5.5 V
3. Applications
LED and 7-segment displays
Simple high-power (500 mA) LED dimming
General purpose output
Instrumentation indicators
NXP Semiconductors
PCA9621
65 mA 8-bit 2-wire bus output port
4. Ordering information
Table 1.
Ordering information
T
amb
=
−
40 to +85
°
C.
Type number
PCA9621D
PCA9621PW
Topside
mark
PCA9621
PCA9621
Package
Name
SO16
TSSOP16
Description
plastic small outline package; 16 leads; body width 3.9 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT403-1
5. Block diagram
2.7 V to 5.5 V
R1
R2
V
DD
R3
R4
R5
R6
PCA9621
SCL 14
SDA 15
FILTER
16
4
5
6
P0
P1
P2
P3
P4
P5
P6
P7
R7
R8
R9
R10
LED
LED
high
current
LED
RESET
A0
A1
A2
3
1
2
13
I
2
C-BUS SLAVE
TRANSCEIVER
7
9
10
11
12
output
output
8
V
SS
002aaf379
Fig 1.
Block diagram of PCA9621
PCA9621
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 9 March 2011
2 of 18
NXP Semiconductors
PCA9621
65 mA 8-bit 2-wire bus output port
6. Pinning information
6.1 Pinning
A0
A1
RESET
P0
P1
P2
P3
V
SS
1
2
3
4
16 V
DD
15 SDA
14 SCL
13 A2
A0
A1
RESET
P0
P1
P2
P3
V
SS
1
2
3
4
5
6
7
8
002aaf382
16 V
DD
15 SDA
14 SCL
13 A2
12 P7
11 P6
10 P5
9
P4
PCA9621D
5
6
7
8
002aaf381
12 P7
11 P6
10 P5
9
P4
PCA9621PW
Fig 2.
Pin configuration for SO16
Fig 3.
Pin configuration for TSSOP16
6.2 Pin description
Table 2.
Symbol
A0
A1
RESET
P0
P1
P2
P3
V
SS
P4
P5
P6
P7
A2
SCL
SDA
V
DD
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
address input 0
address input 1
active LOW reset input
output port 0
output port 1
output port 2
output port 3
negative supply (ground)
output port 4
output port 5
output port 6
output port 7
address input 2
serial clock line
serial data line
positive supply
PCA9621
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 9 March 2011
3 of 18
NXP Semiconductors
PCA9621
65 mA 8-bit 2-wire bus output port
7. Functional description
Refer to
Figure 1 “Block diagram of PCA9621”.
7.1 V
DD
, V
SS
— DC supply pins
The power supply voltage for the PCA9621 may be any voltage in the range 2.7 V to
5.5 V. All other I/Os are clamped to V
DD
and V
SS
through ESD protection diodes.
7.2 SCL, SDA — 2-wire bus interface
The state of the output ports is determined by the Control register, which is set and read
via a 2-wire bus interface using I
2
C-bus style signalling. The interface is Fast-mode Plus
(Fm+) I
2
C-bus compatible, though the ports contain ESD protection diodes to the positive
and negative supplies. Consequently, V
I2C-bus
(voltage at SCL and SDA) must remain
within the V
DD
and V
SS
supply levels.
7.3 P0 to P7 — output ports
There are eight open-drain output ports whose state is determined by the Control register.
Programming a ‘1’ or HIGH to the relevant register bit will turn on the corresponding port,
resulting at a LOW or ‘0’ at the port. In the case of LED driving, this would result in the
LED turning ON.
Programming a ‘0’ or LOW in the register turns off the open-drain port, placing it in a
high-impedance mode.
The ports are protected by ESD diodes to the supplies so they must not be driven above
the V
DD
or below the V
SS
levels.
7.4 RESET — reset IC to default state
The active LOW RESET input is used to disable the buffer and reset it to its default state.
The RESET signal will clear the contents of the Control register, turning off all output
ports, and resetting the state of the I
2
C-bus slave transceiver block.
7.5 Power-On Reset (POR)
During power-on, the PCA9621 is internally held in the reset condition for a maximum of
t
rst
= 500 ns. The default condition after reset is for the Control register to be erased
(all zeros), resulting in all output ports being off (high-impedance).
PCA9621
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 9 March 2011
4 of 18
NXP Semiconductors
PCA9621
65 mA 8-bit 2-wire bus output port
7.6 A0, A1, A2 — address lines
The slave address of the PCA9621 is shown in
Figure 4.
The address pins (A2, A1, A0)
must be driven to a HIGH or LOW level—they are not internally pulled to a default state.
1
1
fixed
0
0
A2
A1
A0 R/W
read = 1
write = 0
002aaf383
externally
selectable
Fig 4.
Slave address
The read/write bit must be set LOW to enable a write to the Control register, or HIGH to
read from the Control register.
7.7 Control register
The Control register of the PCA9621 is shown in
Figure 5.
Each of the four output ports
can be activated independently by setting the appropriate bit in the Control register.
MSB
P7
P6
P5
P4
P3
P2
P1
P0 LSB
002aaf384
1 = ON (sinking)
0 = OFF (high-impedance)
Fig 5.
Control register
A LOW or ‘zero’ bit indicates that the respective channel (P7 to P0) is disabled
(high-impedance). The default reset condition of the register is all zeros, all ports
high-impedance. A HIGH or ‘one’ bit indicates the respective channel is active (sinking).
Example: Programming C1h (1100 0001b) into the Control register results in ports P0, P6
and P7 being ON (sinking) and the remaining ports being OFF (high-impedance).
PCA9621
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 9 March 2011
5 of 18
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