Features
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32-kHz Voltage Regulated Oscillator
1.1 V to 2.2 V Operating-voltage Range
Integrated Capacitors for Digital Trimming
Suitable for up to 12.5 pF Quartz
Trimming Inputs Insenitive to Stray Capacitance
Output Pulse Formers
Mask Options for Motor Period and Pulse Width
Low Resistance Output for Bipolar Stepping Motor
Motor Fast-test Function
Description
The e1467D is an integrated circuit in CMOS Silicon Gate Technology for analog
clocks. It consists of a 32-kHz oscillator, frequency divider, output pulse formers,
push-pull motor drivers and alarm output. Integrated capacitors are mask-selectable
to accomodate the external quartz crystal. Additional capacitance can be selected
through pad bonding to trimming the oscillator frequency.
32-kHz Clock
CMOS IC with
Digital
Trimming and
Alarm
e1467D
4732A–CLOCK–06/03
1
e1467D
Functional Descripion
Oscillator
An oscillator inverter with feedback resistor is provided to generate the 32768 Hz clock fre-
quency. Values for the fixed capacitors at OSCIN and OSCOUT are mask-selectable (see
note 3 of “Operating Characteristics”). Four control inputs, SC1 to SC4, enable the users to
add integrated trimming capacitors to OSCIN and OSCOUT, providing 15 tuning steps.
A frequency variation of typically 4 ppm for each tuning step is obtained by bonding the capac-
itor pads to OSCIN. As none of these pads are bonded, the IC is in an untrimmed state. Figure
2 shows the trimming curve characteristic.
Note:
For applications which utilize this integrated trimming feature, Atmel will determine optimum val-
ues for the integrated capacitors C
OSCIN
and C
OSCOUT
.
Motor Drive
Output
The e1467D contains two push-pull output buffers for driving bipolar stepping motors. During a
motor pulse, the N-channel device of one buffer and the P-channel device of the other buffer
will be activated. Both N-channel transistors are on and conducting between output pulses.
The outputs are protected against inductive voltage spikes with diodes to both supply pins.
The motor output period and pulse width are mask-programmable, as listed below:
Available motor periods (T
M
): 125, 250, 500 ms and 2, 16 s
Available maximum pulse widths (t
M
): 15, 6, 23.4, 31.25, 46.9 ms
Available motor periods for motor test (T
MT
): 250, 500 ms and 1 s
Note:
The following constraints for combination of motor period and pulse widths have to be consid-
ered: T
M
> 4
´
t
M
, T
MT
> 4
´
t
M
or alternatively T
M
= 2
´
t
M
, T
MT
= 2
´
t
M
Alarm Outputs
The alarm output driver consists of a push-pull stage for driving a speaker via an external bipo-
lar transistor. The output is configured for NPN and PNP bipolar capability. The output is an
alarm tone, modulated by a low frequency. Tone frequencies, modulation frequencies, and
on/off times are selectable via the metal mask option.
A debounced alarm input is provided. Alarm activation is connected either to V
DD
or V
SS
by a
mask option.
For test purposes, the TEST pad is open. With a high resistance probe (R
³
10 M
W
,
C
³
20 pF), a test frequency f
TEST
of 128 Hz can be measured at the ALIN/MTEST pad. Con-
necting ALIN/MTEST (for at least 32 ms) to the opposite polarity for alarm activation changes
the motor period from the selected value to T
MT
(mask-selectable) while the pulse width
remains unaffected. This feature can be used for testing the mechanical parts of the clock.
Alarm Input
Test Functions
3
4732A–CLOCK–06/03
Figure 2.
Functional Test
VDD
SC4
SC3
SC2
SC1
VDD
VSS
1
2
13 12 11 10
9
8
OSCIN
OSCOUT
ALOUT
MOT2
3
4
6
5
R
3
e1467D
ALIN/
-MT
7
R
1
MOT1R
VSS
MOT1L
R
2
Test Crystal
Specification
Oscillation frequency
Series resistance
Static capacitance
Dynamic capacitance
Load capacitance
f
OSC
= 32768 Hz
R
S
= 30 k
W
C
0
= 1.5 pF
C
1
= 3.0 fF
C
L
optionally 10 or 12.5 pF
Absolute Maximum Ratings
Absolute maximum ratings define parameter limits which, if exceeded, may permanently change or damage the device.
All inputs and outputs on Atmel’s circuits are protected against electrostatic discharges. However, precautions to minimize
the build-up of electrostatic charges during handling are recommended.
The circuit is protected against supply voltage reversal for typically 5 minutes.
Parameters
Supply voltage
Input voltage range, all inputs
Output short circuit duration
Power dissipation (DIL package)
Operating ambient temperature range
Storage temperature range
Lead temperature during soldering at 2 mm distance, 10 s
P
tot
T
amb
T
stg
T
sld
Symbol
V
SS
V
IN
Value
-0.3 to 5 V
(V
SS
- 0.3 V)
£
V
IN
£
(V
DD
+ 0.3 V)
indefinite
125
-20 to +70
-40 to +125
260
Unit
V
V
mW
°C
°C
°C
4
e1467D
4732A–CLOCK–06/03
e1467D
Operating Characteristics
V
SS
= 0 V, V
DD
= 1.5 V, T
amb
= +25°C, unless otherwise specified.
All voltage levels are measured with reference to V
SS
. Test crystal as specified below.
Parameters
Operating voltage
Operating temperature
Operating current
R
1
=
¥
(2)
V
DD
= 1.2 V, R
1
= 200
W
Test Conditions
Symbol
V
DD
T
amb
I
DD
I
M
T
M
T
MT
t
M
Min.
1.1
-20
Typ.
1.5
1
Max.
2.2
+70
3
Unit
V
°C
µA
mA
Motor Drive Output
Motor output current
Motor period
Motor period during motor test
Motor pulse width
±4.3
See option list
See option list
See option list
1.2
0.1
See option list
See option list
1
0.05
5
0.15
25
0.5
2.2
0.2
s
ms
ms
V
ppm
pF
pF
µA
µA
Oscillator
Start-up voltage
Frequency stability
Integrated input capacitance
Integrated output capacitance
Input current SC1 to SC4
V
IN
= 0.2 V
V
IN
= V
DD(5)
Within 2 s
DV
DD
= 100 mV, V
DD
= 1.1 to 2.2 V
(3)
V
START
Df/f
C
OSCIN
C
OSCOUT
I
SCINL
I
SCINH
Alarm/Output
Output current for driving npn transistor V
DD
= 1.2 V
N-channel
P-channel
N-channel
P-channel
R
3
= 100 kW
R
2
= 1 kW
(2)(4)
R
3
= 1 kW
R
2
= 100 kW
(2)(4)
I
ANn
I
ANp
I
APn
I
APp
f
A
f
MOD
t
ON
/t
OFF
ALIN = V
DD
, peak current
ALIN = V
SS
, peak current
I
AINH
I
AINL
t
AIN
0.6
-0.6
23.4
1
-0.5
0.5
-1
3
-1
1
-2
See option list
See option list
See option list
3
-3
10
-10
31.2
-10
10
µA
mA
mA
µA
Hz
Hz
s
µA
µA
ms
Output current for driving pnp-transistor V
DD
= 1.2 V
Alarm Options
Tone frequency
Modulation frequency
On/off time
Alarm Input/Motor Test
Input current
Input current
Input debounce delay
Notes:
1.
2.
3.
4.
5.
Typical parameters represent the statistical mean values
See test circuit
Values can be selected in 1 pF steps. A total capacitance (C
OSCIN
+ C
OSCOUT
) of 38 pF is available
NPN or PNP driving transistors defined by mask options
I
SCINH
is the peak current of a pulsed current with a duty cycle of 1:63. Average current is always smaller than 10 nA
5
4732A–CLOCK–06/03
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