PRELIMINARY
CYWUSB6935
WirelessUSB™ LR 2.4-GHz DSSS Radio SoC
1.0
Features
2.0
Functional Description
• 2.4-GHz radio transceiver
• Operates in the unlicensed Industrial, Scientific, and
Medical (ISM) band (2.4 GHz–2.483 GHz)
• –95-dBm receive sensitivity
• Up to 0dBm output power
• Range of up to 50 meters or more
• Data throughput of up to 62.5 kbits/sec
• Highly integrated low cost, minimal number of external
components required
• Dual DSSS reconfigurable baseband correlators
• SPI microcontroller interface (up to 2-MHz data rate)
• 13-MHz input clock operation
• Low standby current < 1 µA
• Integrated 32-bit Manufacturing ID
• Operating voltage from 2.7V to 3.6V
• Operating temperature from –40° to 85°C
• Offered in a small footprint 48 QFN or cost saving 28
SOIC
The CYWUSB6935 transceiver is a single-chip 2.4-GHz Direct
Sequence Spread Spectrum (DSSS) Gaussian Frequency
Shift Keying (GFSK) baseband modem radio that connects
directly to a microcontroller.
The CYWUSB6935 is offered in an industrial temperature
range 48-pin QFN, 28-pin SOIC, and a commercial temper-
ature range 48-pin QFN.
3.0
Applications
• Building/Home Automation
— Climate Control
— Lighting Control
— Smart Appliances
— On-Site Paging Systems
— Alarm and Security
• Industrial Control
— Inventory Management
— Factory Automation
— Data Acquisition
• Automatic Meter Reading (AMR)
• Transportation
— Diagnostics
— Remote Keyless Entry
• Consumer / PC
— Locator Alarms
— Presenter Tools
— Remote Controls
— Toys
D IO V A L
D IO
SERDES
A
DSSS
Baseband
A
GFSK
M o d u la to r
RFOUT
IR Q
SS
SCK
M IS O
M OSI
D ig ita l
SERDES
B
DSSS
Baseband
B
GFSK
D e m o d u la to r
R F IN
RESET
PD
S y n th e s iz e r
Figure 3-1. CYWUSB6935 Simplified Block Diagram
X13IN
X13
X13OUT
Cypress Semiconductor Corporation
Document 38-16008 Rev. **
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised February 10, 2004
PRELIMINARY
3.1
Applications Support
The CYWUSB6935 is supported by both the CY3632
WirelessUSB Development Kit and the CY3635 WirelessUSB
N:1 Development Kit. The development kit provides all of the
materials and documents needed to cut the cord on multipoint
to point and point to point low bandwidth high node density
applications including four small form-factor sensor boards
and a hub board that connect to WirelessUSB LR RF module
boards, comprehensive WirelessUSB protocol code examples
and all of the associated schematics, gerber files and bill of
materials. The WirelessUSB N:1 Development Kit is also
supported by the WirelessUSB Listener Tool.
CYWUSB6935
Channel 2x Oversampled, and 32 chips/bit Single Channel
Dual Data Rate (DDR).
4.3.1
64 chips/bit Single Channel
The baseband supports a single data stream operating at
15.625 kbits/sec. The advantage of selecting this mode is its
ability to tolerate a noisy environment. This is because the
15.625 kbits/sec data stream utilizes the longest PN Code
resulting in the highest probability for recovering packets over
the air. This mode can also be selected for systems requiring
data transmissions over longer ranges.
4.3.2
32 chips/bit Dual Channel
4.0
Functional Overview
The CYWUSB6935 provides a complete WirelessUSB LR SPI
to antenna radio modem. The CYWUSB6935 is designed to
implement wireless devices operating in the worldwide 2.4-
GHz Industrial, Scientific, and Medical (ISM) frequency band
(2.400GHz - 2.4835GHz). It is intended for systems compliant
with world-wide regulations covered by ETSI EN 301 489-1
V1.4.1, ETSI EN 300 328-1 V1.3.1 (European Countries);
FCC CFR 47 Part 15 (USA and Industry Canada) and ARIB
STD-T66 (Japan).
The CYWUSB6935 contains a 2.4-GHz radio transceiver, a
GFSK modem and a dual DSSS reconfigurable baseband.
The radio and baseband are both code- and frequency-agile.
Forty-nine spreading codes selected for optimal performance
(Gold codes) are supported across 78 1-MHz channels
yielding a theoretical spectral capacity of 3822 channels. The
CYWUSB6935 supports a range of up to 50 meters or more.
The baseband supports two non-simultaneous data streams
each operating at 31.25 kbits/sec.
4.3.3
32 chips/bit Single Channel 2x Oversampled
The baseband supports a single data stream operating at
31.25 kbits/sec that is sampled twice as much as the other
modes. The advantage of selecting this mode is its ability to
tolerate a noisy environment.
4.3.4
32 chips/bit Single Channel Dual Data Rate (DDR)
The baseband spreads bits in pairs and supports a single data
stream operating at 62.5 kbits/sec.
4.4
Serializer/Deserializer (SERDES)
4.1
2.4-GHz Radio
The receiver and transmitter are a single-conversion low-Inter-
mediate Frequency (low-IF) architecture with fully integrated
IF channel matched filters to achieve high performance in the
presence of interference. An integrated Power Amplifier (PA)
provides an output power control range of 30 dB in seven
steps.
Both the receiver and transmitter integrated Voltage
Controlled Oscillator (VCO) and synthesizer have the agility to
cover the complete 2.4-GHz GFSK radio transmitter ISM
band. The VCO loop filter is also integrated on-chip.
CYWUSB6935 provides a data Serializer/Deserializer
(SERDES), which provides byte-level framing of transmit and
receive data. Bytes for transmission are loaded into the
SERDES and receive bytes are read from the SERDES via the
SPI interface. The SERDES provides double buffering of
transmit and receive data. While one byte is being transmitted
by the radio the next byte can be written to the SERDES data
register insuring there are no breaks in transmitted data.
After a receive byte has been received it is loaded into the
SERDES data register and can be read at any time until the
next byte is received, at which time the old contents of the
SERDES data register will be overwritten.
4.5
Application Interfaces
4.2
GFSK Modem
The transmitter uses a DSP-based vector modulator to
convert the 1-MHz chips to an accurate GFSK carrier.
The receiver uses a fully integrated Frequency Modulator (FM)
detector with automatic data slicer to demodulate the GFSK
signal.
CYWUSB6935 has a fully synchronous SPI slave interface for
connectivity to the application MCU. Configuration and byte-
oriented data transfer can be performed over this interface. An
interrupt is provided to trigger real time events.
An optional SERDES Bypass mode (DIO) is provided for appli-
cations that require a synchronous serial bit-oriented data
path. This interface is for data only.
4.3
Dual DSSS Baseband
4.6
Clocking and Power Management
Data is converted to DSSS chips by a digital spreader. De-
spreading is performed by an oversampled correlator. The
DSSS baseband cancels spurious noise and assembles
properly correlated data bytes.
The DSSS baseband has four operating modes: 64 chips/bit
Single Channel, 32 chips/bit Dual Channel, 32 chips/bit Single
A 13-MHz crystal is directly connected to X13IN and X13
without the need for external capacitors. The CYWUSB6935
has a programmable trim capability for adjusting the on-chip
load capacitance supplied to the crystal. The Radio Frequency
(RF) circuitry has on-chip decoupling capacitors. The
CYWUSB6935 is powered from a 2.7V to 3.6V DC supply. The
CYWUSB6935 can be shutdown to a fully static state using the
PD pin.
Document 38-16008 Rev. **
Page 2 of 32
PRELIMINARY
Below are the requirements for the crystal to be directly
connected to X13IN and X13:
• Nominal Frequency: 13 MHz
• Operating Mode: Fundamental Mode
• Resonance Mode: Parallel Resonant
• Frequency Stability:
±
30 ppm
• Series Resistance:
≤
100 ohms
• Load Capacitance: 10 pF
• Drive Level: 10uW–100 uW
CYWUSB6935
Application Interfaces
SPI Interface
5.0
5.1
The CYWUSB6935 has a four-wire SPI communication
interface between an application MCU and one or more slave
devices. The SPI interface supports single-byte and multi-byte
serial transfers. The four-wire SPI communications interface
consists of Master Out-Slave In (MOSI), Master In-Slave Out
(MISO), Serial Clock (SCK), and Slave Select (SS).
The SPI receives SCK from an application MCU on the SCK
pin. Data from the application MCU is shifted in on the MOSI
pin. Data to the application MCU is shifted out on the MISO
pin. The active-low Slave Select (SS) pin must be asserted to
initiate a SPI transfer.
The application MCU can initiate a SPI data transfer via a
multi-byte transaction. The first byte is the Command/Address
byte, and the following bytes are the data bytes as shown in
Figure 5-1
through
Figure 5-4.
The SS signal should not be
deasserted between bytes. The SPI communications is as
follows:
• Command Direction (bit 7) = “0” Enables SPI read transac-
tion. A “1” enables SPI write transactions.
• Command Increment (bit 6) = “1” Enables SPI auto address
increment. When set, the address field automatically incre-
ments at the end of each data byte in a burst access, oth-
erwise the same address is accessed.
• Six bits of address.
• Eight bits of data.
The SPI communications interface has a burst mechanism,
where the command byte can be followed by as many data
bytes as desired. A burst transaction is terminated by
deasserting the slave select (SS = 1).
The SPI communications interface single read and burst read
sequences are shown in
Figure 5-2
and
Figure 5-3,
respec-
tively.
The SPI communications interface single write and burst write
sequences are shown in
Figure 5-4
and
Figure 5-5,
respec-
tively.
4.7
Receive Signal Strength Indicator (RSSI)
The RSSI register (Reg 0x22) returns the relative signal
strength of the ON-channel signal power and can be used to:
1) determine the connection quality, 2) determine the value of
the noise floor, and 3) check for a quiet channel before trans-
mitting.
The internal RSSI voltage is sampled through a 5-bit analog-
to-digital converter (ADC). A state machine controls the
conversion process. Under normal conditions, the RSSI state
machine initiates a conversion when an ON-channel carrier is
detected and remains above the noise floor for over 50uS. The
conversion produces a 5-bit value in the RSSI register (Reg
0x22, bits 4:0) along with a valid bit, RSSI register (Reg 0x22,
bit 5). The state machine then remains in HALT mode and
does not reset for a new conversion until the receive mode is
toggled off and on. Once a connection has been established,
the RSSI register can be read to determine the relative
connection quality of the channel. A RSSI register value lower
than 10 indicates that the received signal strength is low, a
value greater than 28 indicates a strong signal level.
To check for a quiet channel before transmitting, first set up
receive mode properly and read the RSSI register (Reg 0x22).
If the valid bit is zero, then force the Carrier Detect register
(Reg 0x2F, bit 7=1) to initiate an ADC conversion. Then, wait
greater than 50uS and read the RSSI register again. Next,
clear the Carrier Detect Register (Reg 0x2F, bit 7=0) and turn
the receiver OFF. Measuring the noise floor of a quiet channel
is inherently a 'noisy' process so, for best results, this
procedure should be repeated several times (~20) to compute
an average noise floor level. A RSSI register value of 0-10
indicates a channel that is relatively quiet. A RSSI register
value greater than 10 indicates the channel is probably being
used. A RSSI register value greater than 28 indicates the
presence of a strong signal.
Document 38-16008 Rev. **
Page 3 of 32
PRELIMINARY
Byte 1
Bit #
Bit Name
7
DIR
6
INC
[5:0]
Address
[7:0]
Data
CYWUSB6935
Byte 1+N
Figure 5-1. SPI Transaction Format
SCK
SS
cm d
MOSI
M IS O
D IR
addr
A5
A4
A3
A2
A1
A0
0
IN C
0
d a ta t o m c u
D7
D6
D5
D4
D3
D2
D1
D0
Figure 5-2. SPI Single Read Sequence
SCK
SS
cm d
MOSI
M IS O
D IR
addr
A5
A4
A3
A2
A1
A0
0
IN C
1
d a ta to m c u
D7
D6
D5
D4
D3
D2
1
D1
D0
D7
d a ta to m c u
D6
D5
D4
D3
D2
1+N
D1
D0
Figure 5-3. SPI Burst Read Sequence
SCK
SS
cm d
M O SI
M ISO
DIR
addr
A5
A4
A3
A2
A1
A0
D7
data from m cu
D6
D5
D4
D3
D2
D1
D0
1
INC
0
Figure 5-4. SPI Single Write Sequence
SCK
SS
cm d
MOSI
M IS O
D IR
a dd r
A5
A4
A3
A2
A1
A0
D7
d ata fro m m cu
D6
D5
D4
D3
D2
1
D1
D0
D7
da ta from m cu
D6
D5
D4
D3
D2
1+N
D1
D0
1
IN C
1
Figure 5-5. SPI Burst Write Sequence
Document 38-16008 Rev. **
Page 4 of 32
PRELIMINARY
5.2
DIO Interface
The DIO communications interface is an optional SERDES
bypass data-only transfer interface. In receive mode, DIO and
DIOVAL are valid after the falling edge of IRQ, which clocks
CYWUSB6935
the data as shown in
Figure 5-6
. In transmit mode, DIO and
DIOVAL are sampled on the falling edge of the IRQ, which
clocks the data as shown in
Figure 5-7
. The application MCU
samples the DIO and DIOVAL on the rising edge of IRQ.
IRQ
DIOVAL
DIO
v0
v1
v2
v3
v4
v5
v6
v7
v8
v9
v10
v11
v12
v13
v14
v...
data to mcu
d0
d1
d2
d3
d4
d5
d6
d7
d8
d9
d10
d11
d12
d13
d14
d...
Figure 5-6. DIO Receive Sequence
IRQ
DIOVAL
DIO
v0
v1
v2
v3
v4
v5
v6
v7
v8
v9
v10
v11
v12
v13
v14
v...
data from mcu
d0
d1
d2
d3
d4
d5
d6
d7
d8
d9
d10
d11
d12
d13
d14
d...
Figure 5-7. DIO Transmit Sequence
5.3
Interrupts
The CYWUSB6935 features three sets of interrupts: transmit,
received, and a wake interrupt. These interrupts all share a
single pin (IRQ), but can be independently enabled/disabled.
In transmit mode, all receive interrupts are automatically
disabled, and in transmit mode all receive interrupts are
automatically disabled. However, the contents of the enable
registers are preserved when switching between transmit and
receive modes.
Interrupts are enabled and the status read through 6 registers:
Receive Interrupt Enable (Reg 0x07), Receive Interrupt Status
(Reg 0x08), Transmit Interrupt Enable (Reg 0x0D), Transmit
Interrupt Status (Reg 0x0E), Wake Enable (Reg 0x1C), Wake
Status (Reg 0x1D).
If more than 1 interrupt is enabled at any time, it is necessary
to read the relevant interrupt status register to determine which
event caused the IRQ pin to assert. Even when a given
interrupt source is disabled, the status of the condition that
would otherwise cause an interrupt can be determined by
reading the appropriate interrupt status register. It is therefore
possible to use the devices without making use of the IRQ pin
at all. Firmware can poll the interrupt status register(s) to wait
for an event, rather than using the IRQ pin.
The polarity of all interrupts can be set by writing to the Config-
uration register (Reg 0x05), and it is possible to configure the
IRQ pin to be open drain (if active low) or open source (if active
high).
5.3.1
Wake Interrupt
interrupt indicates that the oscillator has started, and that the
device is ready to receive SPI transfers.
The wake interrupt is enabled by setting bit 0 of the Wake
Enable register (Reg 0x1C, bit 0=1). Whether or not a wake
interrupt is pending is indicated by the state of bit 0 of the Wake
Status register (Reg 0x1D, bit 0). Reading the Wake Status
register (Reg 0x1D) clears the interrupt.
5.3.2
Transmit Interrupts
Four interrupts are provided to flag the occurrence of transmit
events. The interrupts are enabled by writing to the Transmit
Interrupt Enable register (Reg 0x0D), and their status may be
determined by reading the Transmit Interrupt Status register
(Reg 0x0E). If more than 1 interrupt is enabled, it is necessary
to read the Transmit Interrupt Status register (Reg 0x0E) to
determine which event caused the IRQ pin to assert.
The function and operation of these interrupts are described in
detail in
Section 7.0
.
5.3.3
Receive Interrupts
When the PD pin is low, the oscillator is stopped. After PD is
deasserted, the oscillator takes time to start, and until it has
done so, it is not safe to use the SPI interface. The wake
Eight interrupts are provided to flag the occurrence of receive
events, four each for SERDES A and B. In 64 chips/bit and 32
chips/bit DDR modes, only the SERDES A interrupts are
available, and the SERDES B interrupts will never trigger,
even if enabled. The interrupts are enabled by writing to the
Receive Interrupt Enable register (Reg 0x07), and their status
may be determined by reading the Receive Interrupt Status
register (Reg 0x08). If more than one interrupt is enabled, it is
necessary to read the Receive Interrupt Status register (Reg
0x08) to determine which event caused the IRQ pin to assert.
The function and operation of these interrupts are described in
detail in
Section 7.0
.
Document 38-16008 Rev. **
Page 5 of 32
Making friends through disassembly
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