SIT3907AI-D2-33NE-77.760000T datasheet, PDF

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SIT3907AI-D2-33NE-77.760000T: DescriptionOSC DCXO 77.7600MHZ LVCMOS LVTTL; CategoryPassive components; File Size419KB，10 Pages; ManufacturerSiTime; Environmental Compliance

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SIT3907AI-D2-33NE-77.760000T Overview

OSC DCXO 77.7600MHZ LVCMOS LVTTL

SIT3907AI-D2-33NE-77.760000T Parametric

Parameter Name	Attribute value
type	DCXO
frequency	77.76MHz
Function	-
output	LVCMOS，LVTTL
Voltage - Power	3.3V
frequency stability	±25ppm
Operating temperature	-40°C ~ 85°C
Current - Power (maximum)	34mA
grade	-
Installation type	surface mount
Package/casing	6-SMD, no leads
size/dimensions	0.276" long x 0.197" wide (7.00mm x 5.00mm)
Height - Installation (maximum)	0.039"（1.00mm）
Current - Power (disabled) (maximum)	-

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SiT3907

High Precision Digitally Controlled Oscillator (DCXO)

The Smart Timing Choice

Features



Applications



Factory programmable between 1 MHz and 220 MHz

Digitally controlled pull range: ±25, ±50, ±100, ±200, ±400, ±800,

±1600 PPM

Eliminate the need for an external DAC

Superior pull range linearity of <= 0.01%

LVCMOS/LVTTL compatible output

Three industry-standard packages: 3.2 mm x2.5 mm (4-pin), 5.0 mm

x 3.2 mm (6-pin), 7.0 mm x 5.0 mm (6-pin)

Programmable drive strength to reduce EMI

Outstanding silicon reliability of 2 FIT

Ideal for clock synchronization, instrumentation, low

bandwidth PLL, jitter cleaner, clock recovery, audio,

video, and FPGA



Electrical Characteristics

Parameters

Output Frequency Range

Frequency Stability

Symbol

F_stab

F_aging

T_use

Min.

-10

-25

-50

Aging

Operating Temperature Range

-5

-20

-40

1.71

Supply Voltage

Vdd

2.25

2.52

2.97

Pull Range

Linearity

Frequency Change Polarity

Frequency Update Rate

Current Consumption

Duty Cycle

Rise/Fall Time

Output High Voltage

Output Low Voltage

Output Load

Start-up Time

Input Low Voltage

Input Middle Voltage

Input High Voltage

Input High or Low Logic Pulse

Input Middle Pulse Width

Input Impedance

Input Capacitance

RMS period Jitter

RMS Phase Jitter (random)

Lin

–

F_update

Idd

Tr, Tf

VOH

VOL

T_start

VIL

VIM

VIH

T_logic

T_middle

Zin

Cin

T_jitt

T_phj

–

0.4xVdd

0.8xVdd

500

100

–

Typ.

–

1.8

2.5

2.8

3.3

±400, ±800, ±1600

–

Positive Slope

–

1.2

–

1.5

0.6

0.65

12.5

–

0.2xVdd

0.6xVdd

–

0.01

Max.

220

+10

+25

+50

+70

+85

1.89

2.75

3.08

3.63

Unit

MHz

PPM

°C

PPM

–

kU / s

%Vdd

kΩ

20% to 80%

f = 20 MHz, all Vdds

f = 20 MHz, Integration bandwidth = 12 kHz to 20 MHz,

all Vdds. No activity on DP pin.

With full activity on DP pin.

See Figure 5

Frequency control mode 1, see Table 1

Frequency control mode 2, see Table 2

No load condition, f = 100 MHz, Vdd = 2.5V, 2.8V or 3.3V

No load condition, f = 100 MHz, Vdd = 1.8 V

Vdd = 1.8V, 2.5V, 2.8V or 3.3V

Vdd =1.8V, 2.5V, 2.8V or 3.3V, 10% - 90% Vdd level

IOH = -6mA, Vdd = 3.3V, 2.8V, 2.5V

IOL = -3mA, Vdd = 1.8V

IOH = -6mA, Vdd = 3.3V, 2.8V, 2.5V

IOL = -3mA, Vdd = 1.8V

See the last page for Absolute Pull Range, APR table

10 years

Extended Commercial

Industrial

Inclusive of initial tolerance, operating temperature, rated

power, supply voltage and load change

Condition

±25, ±50, ±100, ±200

Notes:

1. Absolute Pull Range (APR) is defined as the guaranteed pull range over temperature and voltage.

2. APR = pull range (PR) - frequency stability (F_stab) - Aging (F_aging)

SiTime Corporation

Rev. 1.2

990 Almanor Avenue

Sunnyvale, CA 94085

(408) 328-4400

www.sitime.com

Revised July 24, 2014

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