24AA52/24LCS52
2K 2.2V I
2
C
™
Serial EEPROM with Software Write-Protect
Device Selection Table
Part
Number
24AA52
24LCS52
Note 1:
V
CC
Range
1.8-5.5
2.2-5.5
Max Clock
Frequency
400 kHz
(1)
400 kHz
Temp
Ranges
I
I
Description:
The Microchip Technology Inc. 24AA52/24LCS52
(24XXX52*) is a 2 Kbit Electrically Erasable PROM
capable of operation across a broad voltage range
(1.8V to 5.5V). This device has a software write-protect
feature for the lower half of the array, as well as an
external pin that can be used to write-protect the entire
array. The software write-protect feature is enabled by
sending the device a special command. Once this
feature has been enabled, it cannot be reversed. In
addition to the software protect feature, there is a WP
pin that can be used to write-protect the entire array,
regardless of whether the software write-protect
register has been written or not. This allows the system
designer to protect none, half, or all of the array,
depending on the application. The device is organized
as one block of 256 x 8-bit memory with a 2-wire serial
interface. Low-voltage design permits operation down
to 1.8V, with standby and active currents of only 1
A
and 1 mA, respectively. The 24XXX52 also has a page
write capability for up to 16 bytes of data. The 24XXX52
is available in the standard 8-pin PDIP, surface mount
SOIC, TSSOP, MSOP, DFN and TDFN packages.
100 kHz for V
CC
<2.2V
Features:
• Single Supply with Operation Down to 1.8V
• Low-Power CMOS Technology:
- 1 mA active current, typical
- 1
A
standby current, typical (I-temp)
• Organized as 1 Block of 256 Bytes (256 x 8)
• Software Write Protection for Lower 128 Bytes
• Hardware Write Protection for Entire Array
• 2-Wire Serial Interface Bus, I
2
C™ Compatible
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz (24AA52) and 400 kHz (24LCS52)
Compatibility
• Self-Timed Write Cycle (including auto-erase)
• Page Write Buffer for up to 16 Bytes
• ESD Protection > 4,000V
• 1,000,000 Erase/Write Cycles
• Data Retention > 200 Years
• 8-Lead PDIP, SOIC, TSSOP, MSOP, DFN and
TDFN Packages
• Pb-Free Finishes Available
• Available for Extended Temperature Ranges:
- Industrial (I): -40°C to +85°C
Block Diagram
A0 A1 A2
WP
HV Generator
Software write
protected area
(00h-7Fh)
Standard
Array
I/O
Control
Logic
Memory
Control
Logic
XDEC
SDA SCL
V
CC
V
SS
Package Types
PDIP/SOIC/TSSOP/MSOP/DFN/TDFN
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
Write-Protect
Circuitry
YDEC
Sense Amp.
R/W Control
A0 1
A1 2
A2 3
V
SS
4
8 V
CC
7 WP
6 SCL
5 SDA
*24XXX52 is used in this document as a generic part number
for the 24AA52/24LCS52 devices.
1996-2011 Microchip Technology Inc.
DS21166K-page 1
24AA52/24LCS52
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.3V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins
4 kV
† NOTICE:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
DC SPECIFICATIONS
V
CC
= +1.8V to +5.5V
Industrial (I): T
A
= -40°C to +85°C
Min
—
0.7 V
CC
—
0.05 V
CC
—
—
—
—
—
—
Standby current
—
—
Typ
—
—
—
—
—
—
—
—
1.0
0.20
0.36
—
Max
—
—
0.3 V
CC
—
0.40
±1
±1
10
3.0
1.0
1.0
—
Units
—
V
V
V
V
A
A
pF
mA
mA
A
—
—
0.2 V
CC
for V
CC
< 2.5V
(Note)
I
OL
= 3.0 mA, V
CC
= 2.5V
V
IN
= V
SS
or V
CC
V
OUT
= V
SS
or V
CC
V
CC
= 5.0V
(Note)
T
A
= 25°C, F
CLK
= 1 MHz
V
CC
= 5.5V, SCL = 400 kHz
—
Industrial
SDA = SCL = V
CC
A0, A1, A2, WP = V
SS
Conditions
DC CHARACTERISTICS
Param.
Symbol
No.
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
V
IH
—
V
IL
V
HYS
V
OL
I
LI
I
LO
C
IN
,
C
OUT
I
CC
read
I
CCS
Characteristic
A0, A1, A2, SCL, SDA
and WP pins
High-level input voltage
Low-level input voltage
Hysteresis of Schmitt
Trigger inputs
Low-level output voltage
Input leakage current
Output leakage current
Pin capacitance
(all inputs/outputs)
I
CC
write Operating current
Note:
This parameter is periodically sampled and not 100% tested.
DS21166K-page 2
1996-2011 Microchip Technology Inc.
24AA52/24LCS52
TABLE 1-2:
AC SPECIFICATIONS
V
CC
= +1.8V to +5.5V
Industrial (I): T
A
= -40°C to +85°C
Min
—
—
600
4000
1300
4700
—
—
—
600
4000
600
4700
0
100
250
600
4000
—
—
1300
4700
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
400
100
—
—
—
—
300
1000
300
—
—
—
—
—
—
—
—
—
900
3500
—
—
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
2.2V
V
CC
5.5V
1.8V
V
CC
2.5V (24AA52)
2.2V
V
CC
5.5V
1.8V
V
CC
2.5V (24AA52)
2.2V
V
CC
5.5V
1.8V
V
CC
2.5V (24AA52)
2.2V
V
CC
5.5V
1.8V
V
CC
2.5V (24AA52)
(Note 1)
2.2V
V
CC
5.5V
1.8V
V
CC
2.5V (24AA52)
2.2V
V
CC
5.5V
1.8V
V
CC
2.5V (24AA52)
(Note 2)
2.2V
V
CC
5.5V
1.8V
V
CC
2.5V (24AA52)
2.2V
V
CC
5.5V
1.8V
V
CC
2.5V (24AA52)
2.2V
V
CC
5.5V
1.8V
V
CC
2.5V (24AA52)
2.2V
V
CC
5.5V
1.8V
V
CC
2.5V (24AA52)
AC CHARACTERISTICS
Param.
Symbol
No.
1
2
3
4
5
6
7
8
9
10
11
12
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:
STA
T
SU
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
Characteristic
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
(Note 1)
SDA and SCL fall time
Start condition hold time
Start condition setup
time
Data input hold time
Data input setup time
Stop condition setup
time
Output valid from clock
(Note 2)
Bus free time: Time the
bus must be free before
a new transmission can
start
13
T
OF
Output fall time from V
IH
20 + 0.1 C
B
minimum to V
IL
—
maximum
Input filter spike
suppression
(SDA and SCL pins)
Write cycle time
(byte or page)
Endurance
—
—
—
—
250
250
50
ns
2.2V
V
CC
5.5V
1.8V
V
CC
2.5V (24AA52)
(Note 1 and Note 3)
14
T
SP
ns
15
16
T
WC
—
—
1M
—
—
5
—
ms
—
cycles 25°C, V
CC
= 5.0V
(Note 4)
Note 1:
Not 100% tested. C
B
= total capacitance of one bus line in pF.
2:
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3:
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a T
I
specification for standard operation.
4:
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site
at www.microchip.com.
1996-2011 Microchip Technology Inc.
DS21166K-page 3
24AA52/24LCS52
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Symbol
A0
A1
A2
V
SS
SDA
SCL
WP
V
CC
Note 1:
PIN FUNCTION TABLE
PDIP
1
2
3
4
5
6
7
8
SOIC
1
2
3
4
5
6
7
8
TSSOP
1
2
3
4
5
6
7
8
MSOP
1
2
3
4
5
6
7
8
DFN
(1)
1
2
3
4
5
6
7
8
TDFN
(1)
1
2
3
4
5
6
7
8
Description
Chip Address Input
Chip Address Input
Chip Address Input
Ground
Serial Address/Data I/O
Serial Clock
Write-Protect Input
+1.8V to 5.5V Power Supply
The exposed pad on the DFN/TDFN packages can be connected to V
SS
or left floating.
2.1
A0, A1, A2
2.3
Serial Clock (SCL)
The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.
Up to eight 24XXX52 devices may be connected to the
same bus by using different Chip Select bit
combinations. These inputs must be connected to
either V
SS
or V
CC
.
This input is used to synchronize the data transfer to
and from the device.
2.4
Write-Protect (WP)
2.2
Serial Address/Data Input/Output
(SDA)
This is the hardware write-protect pin. It can be tied to
V
CC
or V
SS
. If tied to V
CC
, the hardware write protection
is enabled. If the WP pin is tied to V
SS
, the hardware
write protection is disabled.
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal. Therefore, the SDA bus requires a pull-
up resistor to V
CC
(typical 10 k for 100 kHz, 2 k for
400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
1996-2011 Microchip Technology Inc.
DS21166K-page 5
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