MWCT1014SFVLH datasheet, PDF - EEWORLD Datasheet

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MWCT1014SFVLH: DescriptionWCT1014SF 64 LQFP; Categorysemiconductor Power management; File Size1MB，65 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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WCT1014SF 64 LQFP

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NXP Semiconductors

Data Sheet: Advance Information

Document Number MWCT101xSF

Rev. 2, 07/2018

MWCT101XS Data Sheet

Key Features

• Operating characteristics

– Voltage range: 2.7 V to 5.5 V

– Ambient temperature range: -40 °C to 105 °C for

HSRUN mode, -40 °C to 125 °C for RUN mode

• Arm™ Cortex-M4F core, 32-bit CPU

– Supports up to 112 MHz frequency (HSRUN) with

1.25 Dhrystone MIPS per MHz

– Arm Core based on the Armv7 Architecture and

Thumb®-2 ISA

– Integrated Digital Signal Processor (DSP)

– Configurable Nested Vectored Interrupt Controller

(NVIC)

– Single Precision Floating Point Unit (FPU)

• Clock interfaces

– 4 - 40 MHz fast external oscillator (SOSC)

– 48 MHz Fast Internal RC oscillator (FIRC)

– 8 MHz Slow Internal RC oscillator (SIRC)

– 128 kHz Low Power Oscillator (LPO)

– Up to 112 MHz (HSRUN) System Phased Lock

Loop (SPLL)

– Up to 50 MHz DC external square wave input clock

– Real Time Counter (RTC)

• Power management

– Low-power Arm Cortex-M4F core with excellent

energy efficiency

– Power Management Controller (PMC) with multiple

power modes: HSRUN, RUN, STOP, VLPR, and

VLPS. Note: CSEc (Security) or EEPROM writes/

erase will trigger error flags in HSRUN mode (112

MHz) because this use case is not allowed to

execute simultaneously. The device will need to

switch to RUN mode (80 Mhz) to execute CSEc

(Security) or EEPROM writes/erase.

– Clock gating and low power operation supported on

specific peripherals.

MWCT101XSF

• Memory and memory interfaces

– Up to 2 MB program flash memory with ECC

– 64 KB FlexNVM for data flash memory with ECC

and EEPROM emulation. Note: CSEc (Security) or

EEPROM writes/erase will trigger error flags in

HSRUN mode (112 MHz) because this use case is

not allowed to execute simultaneously. The device

will need to switch to RUN mode (80 MHz) to

execute CSEc (Security) or EEPROM writes/erase.

– Up to 256 KB SRAM with ECC

– Up to 4 KB of FlexRAM for use as SRAM or

EEPROM emulation

– Up to 4 KB Code cache to minimize performance

impact of memory access latencies

– QuadSPI with HyperBus™ support

• Mixed-signal analog

– Up to two 12-bit Analog-to-Digital Converter

(ADC) with up to 32 channel analog inputs per

module

– One Analog Comparator (CMP) with internal 8-bit

Digital to Analog Converter (DAC)

• Debug functionality

– Serial Wire JTAG Debug Port (SWJ-DP) combines

– Debug Watchpoint and Trace (DWT)

– Instrumentation Trace Macrocell (ITM)

– Test Port Interface Unit (TPIU)

– Flash Patch and Breakpoint (FPB) Unit

• Human-machine interface (HMI)

– Up to 89 GPIO pins with interrupt functionality

– Non-Maskable Interrupt (NMI)

This document contains information on a pre-production product. Specifications

and pre-production information herein are subject to change without notice.

Table of Contents

Block diagram.................................................................................... 4

Feature comparison............................................................................ 5

Ordering parts.....................................................................................7

3.1 Determining valid orderable parts ............................................ 7

3.2 Ordering information ................................................................ 8

General............................................................................................... 9

4.1 Absolute maximum ratings........................................................9

4.2 Voltage and current operating requirements..............................10

4.3 Thermal operating characteristics..............................................11

4.4 Power and ground pins.............................................................. 11

4.5 LVR, LVD and POR operating requirements............................13

4.6 Power mode transition operating behaviors.............................. 13

4.7 Power consumption................................................................... 14

4.8 ESD handling ratings.................................................................17

4.9 EMC radiated emissions operating behaviors........................... 17

I/O parameters....................................................................................17

5.1 AC electrical characteristics...................................................... 17

5.2 General AC specifications......................................................... 18

5.3 DC electrical specifications at 3.3 V Range.............................. 18

5.4 DC electrical specifications at 5.0 V Range.............................. 19

5.5 AC electrical specifications at 3.3 V range .............................. 20

5.6 AC electrical specifications at 5 V range ................................. 21

5.7 Standard input pin capacitance.................................................. 22

5.8 Device clock specifications....................................................... 22

Peripheral operating requirements and behaviors.............................. 23

6.1 System modules......................................................................... 23

6.2 Clock interface modules............................................................ 23

6.2.1

6.2.2

6.2.3

External System Oscillator electrical specifications....23

External System Oscillator frequency specifications . 25

System Clock Generation (SCG) specifications.......... 26

6.2.3.1

Fast internal RC Oscillator (FIRC)

electrical specifications............................ 26

6.2.3.2

Slow internal RC oscillator (SIRC)

electrical specifications ........................... 26

6.2.4

Low Power Oscillator (LPO) electrical specifications

......................................................................................27

6.4.2

6.3.2

6.3.1.2

6.2.5

SPLL electrical specifications .....................................27

6.3 Memory and memory interfaces................................................27

6.3.1

Flash memory module (FTFC) electrical

specifications................................................................27

6.3.1.1

Flash timing specifications —

commands................................................ 27

Reliability specifications..........................30

QuadSPI AC specifications..........................................31

6.4 Analog modules......................................................................... 35

6.4.1

ADC electrical specifications...................................... 35

6.4.1.1

6.4.1.2

12-bit ADC operating conditions............. 35

12-bit ADC electrical characteristics....... 37

CMP with 8-bit DAC electrical specifications............ 39

6.5 Communication modules........................................................... 43

6.5.1

6.5.2

6.5.3

6.5.4

6.5.5

LPUART electrical specifications............................... 43

LPSPI electrical specifications.................................... 43

LPI2C electrical specifications.................................... 49

FlexCAN electical specifications.................................50

Clockout frequency......................................................50

6.6 Debug modules.......................................................................... 50

6.6.1

6.6.2

6.6.3

SWD electrical specofications .................................... 50

Trace electrical specifications......................................52

JTAG electrical specifications..................................... 53

Thermal attributes.............................................................................. 56

7.1 Description.................................................................................56

7.2 Thermal characteristics..............................................................56

7.3 General notes for specifications at maximum junction

temperature................................................................................ 59

Dimensions.........................................................................................60

8.1 Obtaining package dimensions ................................................. 60

Pinouts................................................................................................61

9.1 Package pinouts and signal descriptions....................................61

10 Revision History.................................................................................61

MWCT101XS Data Sheet, Rev. 2, 07/2018

NXP Semiconductors

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