It
8 BIT SINGLE CHIP MICROCONTROLLER
Preliminary
LC875G16A/12A/08A
LC875G16A
8-Bit Single Chip Microcontroller incorporating 16K-byte ROM and 512-byte RAM on chip.
LC875G12A
8-Bit Single Chip Microcontroller incorporating 12K-byte ROM and 512-byte RAM on chip.
LC875G08A
8-Bit Single Chip Microcontroller incorporating 8K-byte ROM and 512-byte RAM on chip.
Overview
The LC875G16A,LC875G12A,LC875G08A is 8-bit single chip microcontroller with the following one-chip
features:
- CPU : Operable at a minimum bus cycle time of 100ns
- On-chip ROM Maximum Capacity : LC875G16A 16K bytes
LC875G12A 12K bytes
LC875G08A
8K bytes
- On-chip RAM Capacity : 512 bytes
- two high performance 16-bit timer/counters (can be divided into 8 bit timers)
- two 8-bit timers with prescalers
- timer for use as date/time clock
- one synchronous serial I/O port (with automatic block transmit/receive function)
- one asynchronous/synchronous serial I/O port
- 12-bit PWM × 2
- 12-channel × 10-bit AD converter
- high speed clock counter
- system clock divider
- 18-source 10-vectored interrupt system
Features
(1) Read Only Memory (ROM)
- 16384 × 8 bits (LC875G16A)
- 12288 × 8 bits (LC875G12A)
- 8192 × 8 bits (LC875G08A)
(2) Random Access Memory (RAM) : 512 × 9 bit
♦
No products described or contained herein are intended for use in surgical implants, life-support systems,
aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the
like, the failure of which may directly or indirectly cause injury, death or property loss.
♦
Anyone purchasing any products described or contained herein for an above-mentioned use shall:
1) Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates,
subsidiaries and distributors and all their officers and employees, jointly and severally, against any
and all claims and litigation and all damages, cost and expenses associated with such use:
2) Not impose any responsibility for any fault or negligence which may be cited in any such claim or
litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of
their officers and employees jointly or severally.
♦
Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no
guarantees are made or implied regarding its use or any infringements of intellectual property rights or other
rights of third parties.
This catalog provides information as of Apr 2002. Specifications and information herein are subject to change
without notice.
SANYO Electric Co., Ltd. Semiconductor Company. System-Business Div.
1-1-1, Sakata Oizumi-Machi, Gunma, JAPAN
Ver.0.91
Nov 29 Microcomputer Development Div.
H.Ohsawa
1/27
LC875G16A/12A/08A
(3) Bus Cycle Time
- 100ns (10MHz)
Note: Bus cycle time indicates the speed to read ROM.
(4) Minimum Instruction Cycle Time (tCYC) : 300ns (10MHz)
(5) Ports
- Input/output ports
Input/output programmable for each bit individually
Data direction programmable in nibble units
- Input ports
- PWM output ports
- Oscillator pins
- Reset pin
- Power supply
23 (P1n, P2n, P30 to P32, P70 to P73)
8 (P0n)
2 (XT1, XT2)
2 (PWM0, PWM1)
2 (CF1, CF2)
1 (
RES
)
4 (VSS1 to 2, VDD1 to 2)
(6) Timer
- Timer 0 : 16-bit timer/counter with capture register
Mode 0: Two 8-bit timers with programmable 8-bit prescaler and 8-bit capture register
Mode 1: 8-bit timer with 8-bit programmable prescaler and 8-bit capture register + 8-bit
counter with 8-bit capture register
Mode 2: 16-bit timer with 8-bit programmable prescaler and 16-bit capture register
Mode 3: 16-bit counter with 16-bit capture register
- Timer 1 : PWM/16-bit timer/counter with toggle output
Mode 0: 8-bit timer (with toggle output) + 8-bit timer/counter (with toggle output)
Mode 1: Two 8-bit PWM
Mode 2: 16-bit timer/counter (with toggle output) Toggle output is also possible by using the
lower order 8 bits.
Mode 3: 16 bit timer (with toggle output) The lower order 8 bits can be used as PWM output.
- Timer 4: 8-bit timer with 6-bit prescaler
- Timer 5: 8-bit timer with 6-bit prescaler
- Base timer
1. Clock for the base timer is selectable from sub-clock (32.768kHz crystal oscillation), system
clock or programmable prescaler output of timer 0.
2. There can be five separate interrupt sources.
(7) High speed clock counter
1. Maximum of 20MHz possible (when using a 10MHz main clock).
2. Real-time output
(8) Serial interface
- SIO 0: 8 bit synchronous serial interface
1. LSB first/MSB first-function available
2. An internal 8-bit baud-rate generator (maximum transmit clock period 4/3 T
CYC
)
3. Consecutive automatic data communication (1 - 256 bits)
- SIO 1: 8 bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2 - 512 T
CYC
)
Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud-rate 8 - 2048 T
CYC
)
Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2 - 512 T
CYC
)
Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)
2/27
Ver.0.90
LC875G16A/12A/08A
(9) AD converter
- 12-channel × 10-bit AD converter
(10) PWM
- 2 channel × synchronous variable 12 bit PWM
(11) Remote receiver circuit (share with P73/INT3/T0IN terminal)
- Noise rejection function (The filtering time of the noise rejection filter (1T
CYC
/32 T
CYC
/128 T
CYC
) can be
switched by program.)
(12) Watchdog timer
- External RC circuit is required.
- Interrupt or system reset is activated when the timer overflows.
(13) Interrupts
- 18-source and 10-vectored interrupt function:
1. Three interrupt priorities, low (L), high (H) and highest (X) are supported with multi-level nesting
possible. During interrupt handling, an equal or lower level interrupt request is refused.
2. If interrupt requests for two or more vector addresses occur at once, the higher level interrupt
takes precedence. In the case of equal priority levels, the vector with the lowest address takes
precedence.
No.
Vector
Selectable Level
Interrupt signal
1
00003H
X or L
INT0
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4
4
0001BH
H or L
INT3/INT5/Base timer
5
00023H
H or L
T0H
6
0002BH
H or L
T1L/T1H
7
00033H
H or L
SIO0
8
0003BH
H or L
SIO1
9
00043H
H or L
ADC
10
0004BH
H or L
Port 0/T4/T5/PWM0, PWM1
• Priority Level: X > H > L
• For equal priority levels, vector with lowest address takes precedence.
(15) Subroutine stack levels
- A maximum of 1536 levels (set stack inside RAM)
(16) Multiplication and division
- 16 bits × 8 bits (5 instruction-cycle times)
- 24 bits × 16 bits (12 instruction-cycle times)
- 16 bits ÷ 8 bits (8 instruction-cycle times)
- 24 bits ÷ 16 bits (12 instruction-cycle times)
(17) Oscillation circuits
- Built-in RC oscillation circuit used for the system clock
- CF oscillation circuit used for the system clock
- Crystal oscillation circuit used for the system clock
- Built-in frequency variable RC oscillation circuit used for the system clock
(17) System clock divider
- operable on the lowest power consumption
- Minimum instruction cycle time (300ns, 600ns, 1.2µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, 76.8µs can be
switched by program (when using 10MHz main clock)
Ver.0.90
3/27
LC875G16A/12A/08A
(18) Standby function
- HALT mode
The HALT mode stops program execution while the peripheral circuits keep operating and
minimizes power consumption. This operation mode can be released by a system reset or an
interrupt request.
- HOLD mode
The HOLD mode stops program execution and all oscillation circuits: CF, RC and Crystal
oscillations. This mode can be released by the following conditions.
1. Supply "L" level to the reset terminal (
RES
)
2. Supply the selected level to at lease one of INT0, INT1, INT2, INT4 INT5.
3. Supply an interrupt condition to Port 0.
- X’tal HOLD mode
The X’tal HOLD mode stops program execution and all peripheral circuits except for the base timer.
The crystal oscillator maintains its state at HOLD mode inception. This mode can be released by
the following conditions.
1. Supply "L" level to the reset terminal (
RES
).
2. Supply the selected level to at least one of INT0, INT1, INT2, INT4, INT5
3. Supply an interrupt condition to Port 0.
4. Supply an interrupt condition to the base timer circuit.
(19) Shipping form
- DIP42S
- QIP48E
- SQFP48
(20) Development tools
- Evaluation (EVA) chip
: LC876093
- Emulator
: EVA62S + ECB876600A + SUB875G00 + POD42DIP or POD48QFP
- Flash ROM version : LC87F5G32A
4/27
Ver.0.90
LC875G16A/12A/08A
Pin Assignment
・
ＤＩＰ４２Ｓ
P32
P31
P30
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN
P73/INT3/T0IN
RES#
XT1/AN10
XT2/AN11
VSS1
CF1
CF2
VDD1
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
P16/T1PWML
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P27/INT5
P26/INT5
P25/INT5
P24/INT5
P23/INT5
P22/INT5
P21/INT5
P20/INT5
P07/AN7
P06/AN6
P05/AN5
P04/AN4
P03/AN3
P02/AN2
P01/AN1
P00/AN0
VSS2
VDD2
PWM0
PWM1
P17/T1PWMH/BUZ
・
ＳＱＦＰ４８/ＱＩＰ４８Ｅ
36
35
34
33
32
31
30
29
28
27
26
25
P24/INT5
P23/INT4
P22/INT4
P21/INT4
P20/INT4
NC
P07/AN7
P06/AN6
P05/AN5
P04/AN4
P03/AN3
P02/AN2
P25/INT5
P26/INT5
NC
NC
P27/INT5
P32
P31
P30
NC
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
NC
P01/AN1
NC
P00/AN0
VSS2
VDD2
PWM0
PWM1
P17/T1PWMH/BUZ
P16/T1PWML
P15/SCK1
P14/SI1/SB1
Ver.0.90
P73/INT3/T0IN
RES#
XT1/AN10
XT2/AN11
VSS1
CF1
CF2
VDD1
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
1
2
3
4
5
6
7
8
9
10
11
12
5/27
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