DEI1070-DMS datasheet, PDF - EEWORLD Datasheet

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DEI1070-DMS: DescriptionLine Driver, 1 Func, 1 Driver, BICMOS, CDIP8, CERAMIC, SIDE BRAZED, DIP-8; CategoryDrivers and interfaces; File Size243KB，8 Pages; ManufacturerDevice Engineering Incorporated

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DEI1070-DMS Overview

Line Driver, 1 Func, 1 Driver, BICMOS, CDIP8, CERAMIC, SIDE BRAZED, DIP-8

DEI1070-DMS Parametric

Parameter Name	Attribute value
Maker	Device Engineering Incorporated
Parts packaging code	DIP
package instruction	DIP,
Contacts	8
Reach Compliance Code	compliant
ECCN code	EAR99
Is Samacsys	N
Differential output	YES
Number of drives	1
Input properties	STANDARD
Interface integrated circuit type	LINE DRIVER
Interface standards	ARINC 429
JESD-30 code	R-CDIP-T8
Nominal negative supply voltage	-15 V
Number of functions	1
Number of terminals	8
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Certification status	Not Qualified
Maximum receive delay
Maximum seat height	5.334 mm
Maximum supply voltage	16.5 V
Minimum supply voltage	9.5 V
Nominal supply voltage	15 V
surface mount	NO
technology	BICMOS
Temperature level	MILITARY
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	7.62 mm
Base Number Matches	1

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Device

Engineering

Incorporated

385 East Alamo Drive

Chandler, AZ 85225

Phone: (480) 303-0822

Fax: (480) 303-0824

E-mail: admin@deiaz.com

DEI1070, DEI1071, DEI1072

ARINC 429 LINE DRIVER WITH RATE

SELECT

FEATURES

•

TTL/CMOS TO ARINC 429 Line Driver.

•

Rate control input set Hi (100KBS) or Lo (12.5KBS) speed slew rates.

•

Operates from ±9.5V to ±16.5V power supply.

•

Drives full ARINC load.

•

Output resistor options: 0, 10 or 37.5 Ohms.

•

Packages: thermally enhanced 8 lead SOIC and ceramic sidebrazed DIP

•

Outputs Short Circuit Tolerant

GENERAL DESCRIPTION

The DEI1070 family of 8 pin BiCMOS integrated circuits are line drivers designed to directly drive the ARINC 429 avionics

serial digital data bus. The device converts TTL/CMOS serial input data to the tri-level RZ bipolar differential modulation

format of the ARINC bus. A TTL/CMOS control input selects the output slew rate for HI (100KBS) and LOW (12.5KBS)

speed operation. No external timing capacitors are required.

The DEI1070 has internal 37.5 Ohm output resistors, the DEI1071 has 10 Ohm resistors, and the DEI1072 has none. The 10

and 0 Ohm options require external series resistors which are typically used to implement a transient voltage protection

network.

Table 1 PIN DESCRIPTION

HI/LO

TTLIN0

TTLIN1

GND

NAME

HI/LO

TTLIN0

TTLIN1

GND

V-

429OUTA

DESCRIPTION

LOGIC INPUT.

Slew rate control. 1 = Hi speed. 0

= Low speed.

LOGIC INPUT.

Serial digital data input 0.

LOGIC INPUT.

Serial digital data input 1.

POWER INPUT.

Ground.

POWER INPUT.

–9.5 to –16.5 VDC

429 OUTPUT.

ARINC 429 format serial digital data

output A.

429 OUTPUT.

ARINC 429 format serial digital data

output B.

POWER INPUT.

+9.5 to +16.5 VDC.

V+

429OUTB

429OUTA

V-

Note:

Heatsink pad is electrically Isolated.

429OUTB

V+

DS-MW-01070-01 Rev. J

NOT RECOMMENDED FOR NEW DESIGN – Use DEI107XA

11/26/07

Page 1 of 8

DESIGN CONSIDERATIONS

Transient Voltage Protection

External transient voltage suppressing devices are required to protect the device from stress such as that defined by DO160D

Section 22, Lightning Induced Transient Susceptibility. The output stage of the driver includes intrinsic clamp diodes to the

V+ and V- power rails. Consider using the 0 Ohm output option to allow use of an external 36 Ohm current limiting resistor

and transient voltage suppressor. Transients at the device must be limited to less than one diode drop beyond the power rails to

prevent excessive current to the device.

Thermal Management

Device power dissipation varies greatly as a function of data rate, load capacitance, data duty cycle, and supply voltage. Proper

thermal management is important in designs operating at the HI speed data rate (100KBS) with high capacitive loads and high

data duty cycles. Dissipation may be estimated from the graph below which shows the approximate power dissipation for

various loads and supply voltages. It is calculated for 100% data duty cycle at 100KBS with no word gap null times and must

be reduced by the appropriate data duty cycle. Adjust for the application data duty cycle using a factor of (total bits transmitted

in 10 sec period / 1,000,000) = (32 x total ARINC words transmitted in 10 sec period / 1,000,000).

Heat transfer from the IC package should be maximized. Use maximum trace width on all power and signal connections at the

IC. The exposed heat sink pad of the SOIC package should be soldered to a heat spreader land on the PCB. The pad is

electrically isolated. Maximize land size by extending beyond the IC outline if possible. Place vias on the signal/power traces

close to the IC and on the heat spreader land to maximize heat flow to the internal power planes.

429 DRIVER DEVICE POWER DISSIPATION (100kbs, 100% DC)

1.6

1.4

1.2

Power Dissipation (W)

100KHz, Full Load (30nF/400Ohm)

0.8

100KHz, 2/3 Load (20nF/600Ohm)

100KHz, 1/3 Load (10nF/1200Ohm)

0.6

0.4

0.2

Supply Voltage (+ / - V)

DS-MW-01070-01 Rev. J

NOT RECOMMENDED FOR NEW DESIGN – Use DEI107XA

11/26/07

Page 5 of 8

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