PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS853052
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V, 3.3V, 5V LVPECL M
ULTIPLEXER
F
EATURES
•
1 differential 2.5V, 3.3V or 5V LVPECL output
•
2 selectable LVCMOS/LVTTL clock inputs
•
Output frequency: TBD
•
Additive phase jitter, RMS: 0.06ps (typical)
•
Propagation Delay: 370ps (typical)
•
2.5V, 3.3V or 5V operating supply voltage
(operating range 2.375V to 5.5V)
•
-40°C to 85°C ambient operating temperature
•
Pin compatible with MC100EP58
G
ENERAL
D
ESCRIPTION
The ICS853052 is a Dual LVCMOS / LVTTL-to-
Differential 2.5V, 3.3V, 5V LVPECL Multiplexer
HiPerClockS™
and a member of the HiPerClocks™family of High
Performance Clocks Solutions from ICS. The
ICS853052 has two selectable single ended
clock inputs. The single ended clock input accepts LVCMOS
or LVTTL input levels and translates them to 2.5V, 3.3V or 5V
LVPECL levels. The small outline 8-pin TSSOP or 8-pin SOIC
packages make this device ideal for applications where space,
high performance and low power are important.
ICS
B
LOCK
D
IAGRAM
Da
1
nQ
Q
Db
0
P
IN
A
SSIGNMENT
nc
Da
Db
SEL
1
2
3
4
8
7
6
5
V
CC
Q
nQ
V
EE
SEL
ICS853052
8-Lead TSSOP, 118 mil
3mm x 3mm x 0.95mm package body
G Package
Top View
8-Lead SOIC, 150 mil
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
853052AG
www.icst.com/products/hiperclocks.html
REV. A JULY 1, 2004
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS853052
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V, 3.3V, 5V LVPECL M
ULTIPLEXER
Type
Description
No connect.
Pulldown LVCMOS / LVTTL clock inputs.
Select input pin. When HIGH, selects Da input clock.
Pulldown When Low selects Db input clock.
Single-ended 100H LVPECL interface levels.
Negative supply pin.
Differential output pair. LVPECL interface levels.
Positive supply pin.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2, 3
4
5
6, 7
8
Name
nc
Da, Db
SEL
V
EE
nQ, Q
V
CC
Input
Input
Power
Output
Power
Unused
NOTE:
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
1
75
Maximum
Units
pF
KΩ
T
ABLE
3.
SEL
0
1
C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
Selected Source
Db
Da
853052AG
www.icst.com/products/hiperclocks.html
2
REV. A JULY 1, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS853052
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V, 3.3V, 5V LVPECL M
ULTIPLEXER
6V (LVPECL mode, V
EE
= 0)
-6V (ECL mode, V
CC
= 0)
-0.5V to V
CC
+ 0.5 V
0.5V to V
EE
- 0.5V
50mA
100mA
-65°C to 150°C
101.7°C/W (0 m/s) TSSOP
112.7°C/W (0 lfpm) SOIC
NOTE:
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Negative Supply Voltage, V
EE
Inputs, V
I
(LVPECL mode)
Inputs, V
I
(ECL mode)
Outputs, I
O
Continuous Current
Surge Current
Storage Temperature, T
STG
Package Thermal Impedance,
θ
JA
(Junction-to-Ambient)
Operating Temperature Range, TA -40°C to +85°C
T
ABLE
4A. DC C
HARACTERISTICS
,
V
CC
= 2.5V; V
EE
= 0V
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
I
IH
Parameter
Power Supply Current
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage,
Single-Ended
Input Low Voltage,
Single-Ended
Input High Current
1.375
0.605
1.275
0.63
Min
-40°C
Typ
21
1.475
0.745
1.58
0.88
1.56
0.965
150
150
1.425
0.625
1.275
0.63
Max
Min
25°C
Typ
21
1.495
0.72
1.57
0.815
1.56
0.965
150
150
1.495
0.64
1.275
0.63
Max
Min
85°C
Typ
21
1.53
0.735
1.565
0.83
-0.83
0.965
150
Max
Units
mA
V
V
V
V
µA
I
IL
Input Low Current
150
Input and output parameters vary 1:1 with V
CC
.
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
µA
T
ABLE
4B. DC C
HARACTERISTICS
,
V
CC
= 3.3V; V
EE
= 0V
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
I
IH
Parameter
Power Supply Current
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage),
(Single-Ended)
Input Low Voltage,
(Single-Ended)
Input High Current
2175
1405
2075
1355
Min
-40°C
Typ
21
2275
1545
2380
1680
2420
1675
150
150
2225
1425
2075
1355
Max
Min
25°C
Typ
21
2295
1520
2370
1615
2420
1675
150
150
2295
1440
2075
1355
Max
Min
85°C
Typ
21
2330
1535
2365
1630
2420
1675
150
Max
Units
mA
mV
mV
mV
mV
µA
µA
Input Low Current
150
I
IL
Input and output parameters vary 1:1 with V
CC
.
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
853052AG
www.icst.com/products/hiperclocks.html
3
REV. A JULY 1, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS853052
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V, 3.3V, 5V LVPECL M
ULTIPLEXER
-40°C
Typ
21
3875
3105
3775
3055
3975
3245
4105
3380
4120
3375
150
150
4080
3125
3775
3055
25°C
Typ
21
3925
3220
3995
3315
4120
3375
150
150
4070
3140
3775
3055
85°C
Typ
21
3995
3235
4065
3330
4120
3375
150
T
ABLE
4C. DC C
HARACTERISTICS
,
V
CC
= 5V; V
EE
= 0V
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
I
IH
Parameter
Power Supply Current
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage,
Single-Ended
Input Low Voltage,
Single-Ended
Input High Current
Min
Max
Min
Max
Min
Max
Units
mA
mV
mV
mV
mV
µA
µA
Input Low Current
150
I
IL
Input and output parameters vary 1:1 with V
CC
.
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
4D. ECL DC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -5.5V
TO
-2.375V
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
I
IH
Parameter
Power Supply Current
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage,
Single-Ended
Input Low Voltage,
Single-Ended
Input High Current
-1125
-1895
-1225
-1945
Min
-40°C
Typ
21
-1025
-1755
-920
-1620
-880
-1625
150
150
-1075
-1875
-1225
-1945
Max
Min
25°C
Typ
21
-1005
-1780
-930
-1685
-880
-1625
150
150
-1005
-1860
-1225
-1945
Max
Min
85°C
Typ
21
-970
-1765
-935
-1670
-880
-1625
150
Max
Units
mA
mV
mV
mV
mV
µA
µA
I
IL
Input Low Current
150
Input and output parameters vary 1:1 with V
CC
.
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -5.5V
TO
-2.375V
OR
V
CC
= 2.375V
TO
5.5V; V
EE
= 0V
Symbol
f
MAX
Parameter
Output Frequency
Propagation Delay, Low to High;
NOTE 1
Propagation Delay, High to Low;
NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
Input Voltage Swing (Differential)
Output Rise/Fall Time
20% to 80%
-40°C
Min
Typ
TBD
TBD
TBD
TBD
TBD
TBD
Max
Min
25°C
Typ
TBD
370
370
0.06
TBD
180
Max
Min
85°C
Typ
TBD
TBD
TBD
TBD
TBD
TBD
Max
Units
GHz
ps
ps
ps
ps
ps
t
PLH
t
PHL
t
jit
V
PP
t
R
/t
F
All parameters are measured
≤
1GHz unless otherwise noted.
NOTE 1: Measured from V
CC
/2 of the input crossing point to the differential output crossing point.
853052AG
www.icst.com/products/hiperclocks.html
4
REV. A JULY 1, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS853052
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
2.5V, 3.3V, 5V LVPECL M
ULTIPLEXER
A
DDITIVE
P
HASE
J
ITTER
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
-30
-40
-50
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
Input/Output Additive Phase Jitter
@ 155.52MHz (12KHz to 20MHz)
= 0.06ps typical
SSB P
HASE
N
OISE
dBc/H
Z
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
100
-190
1k
10k
100k
1M
10M
100M
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
853052AG
www.icst.com/products/hiperclocks.html
5
REV. A JULY 1, 2004
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