PRELIMINARY
DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
ICS853052
G
ENERAL
D
ESCRIPTION
The ICS853052 is a Dual LVCMOS / LVTTL-to-
Differential 2.5V, 3.3V, 5V LVPECL Multiplexer and
HiPerClockS™
a member of the HiPerClocks™ family of High
Perfor mance Clocks Solutions from IDT. The
ICS853052 has two selectable single ended clock
inputs. The single ended clock input accepts LVCMOS or LVTTL
input levels and translates them to 2.5V, 3.3V or 5V LVPECL
levels. The small outline 8-pin TSSOP or 8-pin SOIC packages
make this device ideal for applications where space, high
performance and low power are important.
F
EATURES
•
One differential 2.5V, 3.3V or 5V LVPECL output
•
Two selectable LVCMOS/LVTTL clock inputs
•
Output frequency: TBD
•
Additive phase jitter, RMS: 0.06ps (typical)
•
Propagation Delay: 370ps (typical)
•
2.5V, 3.3V or 5V operating supply voltage
(operating range 2.375V to 5.5V)
•
-40°C to 85°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
IC
S
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
nc
Da
Db
SEL
Q
nQ
Da
Pulldown
1
1
2
3
4
8
7
6
5
V
CC
Q
nQ
V
EE
ICS853052
8-Lead TSSOP, 118 mil
3mm x 3mm x 0.95mm package body
G Package
Top View
8-Lead SOIC, 150 mil
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
Db
Pulldown
0
SEL
Pulldown
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT
™
/ ICS
™
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
1
ICS853052AG REV. B OCTOBER 24, 2007
ICS853052
DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2, 3
4
5
6, 7
8
Name
nc
Da, Db
SEL
V
EE
nQ, Q
V
CC
Input
Input
Power
Output
Power
Type
Unused
Description
No connect.
Pulldown LVCMOS / LVTTL clock inputs.
Select input pin. When HIGH, selects Da input clock.
Pulldown When Low selects Db input clock.
Single-ended 100H LVPECL interface levels.
Negative supply pin.
Differential output pair. LVPECL interface levels.
Positive supply pin.
NOTE:
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
1
75
Maximum
Units
pF
kΩ
T
ABLE
3.
SEL
0
1
C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
Selected Source
Db
Da
IDT
™
/ ICS
™
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
2
ICS853052AG REV. B OCTOBER 24, 2007
ICS853052
DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
PRELIMINARY
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Negative Supply Voltage, V
EE
Inputs, V
I
(LVPECL mode)
Inputs, V
I
(ECL mode)
Outputs, I
O
Continuous Current
Surge Current
Storage Temperature, T
STG
6V (LVPECL mode, V
EE
= 0)
-6V (ECL mode, V
CC
= 0)
-0.5V to V
CC
+ 0.5 V
0.5V to V
EE
- 0.5V
50mA
100mA
-65°C to 150°C
NOTE:
Stresses beyond those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These
ratings are stress specifications only. Functional operation of
product at these conditions or any conditions beyond those listed
in the
DC Characteristics
or
AC Characteristics
is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Operating Temperature Range, TA -40°C to +85°C
Package Thermal Impedance,
θ
JA
101.7°C/W (0 m/s) TSSOP
(Junction-to-Ambient)
112.7°C/W (0 lfpm) SOIC
T
ABLE
4A. DC C
HARACTERISTICS
,
V
CC
= 2.5V; V
EE
= 0V
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
I
IH
Parameter
Power Supply Current
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage,
Single-Ended
Input Low Voltage, Single-Ended
Input High Current
1.375
0.605
1.275
0.63
Min
-40°C
Typ
21
1.475
0.745
1.58
0.88
1.56
0.965
200
20 0
1.425
0.625
1.275
0.63
Ma x
Min
25°C
Typ
21
1.495
0.72
1.57
0.815
1.56
0.965
200
20 0
1.495
0.64
1.275
0.63
Max
Mi n
85°C
Typ
21
1.53
0.735
1.565
0.83
-0.83
0.965
20 0
Max
Units
mA
V
V
V
V
µA
µA
Input Low Current
200
I
IL
Input and output parameters var y 1:1 with V
CC
.
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
4B. DC C
HARACTERISTICS
,
V
CC
= 3.3V; V
EE
= 0V
Symbol Parameter
I
EE
V
OH
V
OL
V
IH
V
IL
I
IH
Power Supply Current
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage, Single-Ended
Input Low Voltage, Single-Ended
Input High Current
2175
1405
2075
1355
Min
-40°C
Typ
21
2275
1545
2380
1680
2420
1675
200
20 0
2225
1425
2075
1355
Max
Min
25°C
Typ
21
2295
1520
2370
1615
2420
167 5
20 0
20 0
229 5
1440
2075
1355
Max
Min
85°C
Typ
21
2330
1535
2365
1630
2420
1675
20 0
Max
Units
mA
mV
mV
mV
mV
µA
µA
I
IL
Input Low Current
200
Input and output parameters vary 1:1 with V
CC
.
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
IDT
™
/ ICS
™
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
3
ICS853052AG REV. B OCTOBER 24, 2007
ICS853052
DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
PRELIMINARY
T
ABLE
4C. DC C
HARACTERISTICS
,
V
CC
= 5V; V
EE
= 0V
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
I
IH
Parameter
Power Supply Current
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage, Single-Ended
Input Low Voltage, Single-Ended
Input High Current
3875
3105
3775
3055
200
200
Min
-40°C
Typ
21
3975
3245
4105
3380
4120
3375
4080
3125
3775
3055
200
Max
Min
25°C
Typ
21
3925
3220
3995
3315
4120
3375
4070
3140
3775
3055
200
200
Max
Min
85°C
Typ
21
3995
3235
4065
3330
4120
3375
200
Max
Units
mA
mV
mV
mV
mV
µA
µA
Input Low Current
I
IL
Input and output parameters vary 1:1 with V
CC
.
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
4D. ECL DC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -5.5V
TO
-2.375V
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
I
IH
Parameter
Power Supply Current
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage, Single-Ended
Input Low Voltage, Single-Ended
Input High Current
-1125
-1895
-1225
-1945
Min
-40°C
Typ
21
-1025
-1755
-92 0
-1620
-880
-1625
20 0
200
-1075
-1875
-1225
-1945
Max
Min
25°C
Typ
21
-1005
-1780
-930
-1685
-880
-1625
200
200
-1005
-1860
-1225
-1945
Max
Min
85°C
Typ
21
-970
-1765
-935
-1670
-880
-1625
200
Max
Units
mA
mV
mV
mV
mV
µA
µA
Input Low Current
200
I
IL
Input and output parameters vary 1:1 with V
CC
.
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -5.5V
TO
-2.375V
OR
V
CC
= 2.375V
TO
5.5V; V
EE
= 0V
Symbol
f
MAX
Parameter
-40°C
Min
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
TBD
TBD
TBD
TBD
TBD
TB D
Max
Units
GHz
ps
ps
ps
ps
ps
Output Frequency
TBD
TBD
Propagation Delay, Low to High;
t
PLH
TBD
370
NOTE 1
Propagation Delay, High to Low;
TBD
370
t
PHL
NOTE 1
Buffer Additive Phase Jitter,
TBD
0.06
t
ji t
RMS; refer to Additive Phase
Jitter section
V
PP
Input Voltage Swing (Differential)
TBD
TBD
Output
t
R
/t
F
20% to 80%
TBD
180
Rise/Fall Time
All parameters are measured
≤
1GHz unless otherwise noted.
NOTE 1: Measured from V
CC
/2 of the input crossing point to the differential output crossing point.
IDT
™
/ ICS
™
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
4
ICS853052AG REV. B OCTOBER 24, 2007
ICS853052
DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
PRELIMINARY
A
DDITIVE
P
HASE
J
ITTER
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
0
-10
-20
-30
-40
-50
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a
dBc
value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter
@ 155.52MHz
(12kHz to 20MHz) = 0.06ps typical
SSB P
HASE
N
OISE
dBc/H
Z
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
100
-190
1k
10k
100k
1M
10M
100M
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The device
meets the noise floor of what is shown, but can actually be lower.
The phase noise is dependant on the input source and
measurement equipment.
IDT
™
/ ICS
™
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
5
ICS853052AG REV. B OCTOBER 24, 2007
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