Device
Engineering
Incorporated
385 East Alamo Drive
Chandler, AZ 85225
Phone: (480) 303-0822
Fax: (480) 303-0824
E-mail: admin@deiaz.com
DEI1070, DEI1071, DEI1072
ARINC 429 LINE DRIVER WITH RATE
SELECT
FEATURES
•
TTL/CMOS TO ARINC 429 Line Driver.
•
Rate control input set Hi (100KBS) or Lo (12.5KBS) speed slew rates.
•
Operates from ±9.5V to ±16.5V power supply.
•
Drives full ARINC load.
•
Output resistor options: 0, 10 or 37.5 Ohms.
•
Packages: thermally enhanced 8 lead SOIC and ceramic sidebrazed DIP
•
Outputs Short Circuit Tolerant
GENERAL DESCRIPTION
The DEI1070 family of 8 pin BiCMOS integrated circuits are line drivers designed to directly drive the ARINC 429 avionics
serial digital data bus. The device converts TTL/CMOS serial input data to the tri-level RZ bipolar differential modulation
format of the ARINC bus. A TTL/CMOS control input selects the output slew rate for HI (100KBS) and LOW (12.5KBS)
speed operation. No external timing capacitors are required.
The DEI1070 has internal 37.5 Ohm output resistors, the DEI1071 has 10 Ohm resistors, and the DEI1072 has none. The 10
and 0 Ohm options require external series resistors which are typically used to implement a transient voltage protection
network.
Table 1 PIN DESCRIPTION
PIN
1
HI/LO
TTLIN0
TTLIN1
GND
1
8
NAME
HI/LO
TTLIN0
TTLIN1
GND
V-
429OUTA
DESCRIPTION
LOGIC INPUT.
Slew rate control. 1 = Hi speed. 0
= Low speed.
LOGIC INPUT.
Serial digital data input 0.
LOGIC INPUT.
Serial digital data input 1.
POWER INPUT.
Ground.
POWER INPUT.
–9.5 to –16.5 VDC
429 OUTPUT.
ARINC 429 format serial digital data
output A.
429 OUTPUT.
ARINC 429 format serial digital data
output B.
POWER INPUT.
+9.5 to +16.5 VDC.
V+
429OUTB
429OUTA
V-
2
3
4
5
6
2
7
3
6
4
5
Note:
Heatsink pad is electrically Isolated.
7
8
429OUTB
V+
©2007 Device Engineering Inc
DS-MW-01070-01 Rev. J
NOT RECOMMENDED FOR NEW DESIGN – Use DEI107XA
11/26/07
Page 1 of 8
FUNCTIONAL DESCRIPTION
HI/LO
TTLIN1
TTLIN0
INPUT LOGIC
and
LEVEL SHIFT
EDGE
SHAPING
OUTPUT
DRIVERS
429OUTA
429OUTB
Block Diagram
Table 2 Speed Control Function
HI/LO
0
1
OUTPUT TRANSITION TIME
10uS (12.5 KBS data)
1.5uS (100KBS data)
Table 3 Transmit Data Function
TTLIN1
0
0
1
1
TTLIN0
0
1
0
1
429OUTA
0V
-5V
5V
0V
429OUTB
0V
5V
-5V
0V
NOTES
Null output
Zero output
One output
Null output
TTLIN1
TTLIN0
+5
429OUTA
-5
50%
Tskew
+5
429OUTB
50%
-5
+10
Tfall
90%
10%
10%
Trise
90%
Trise
Tfall
Differential
429OUT
(A-B)
-5
Figure 1 Timing Waveforms
©2007 Device Engineering Inc
DS-MW-01070-01 Rev. J
NOT RECOMMENDED FOR NEW DESIGN – Use DEI107XA
11/26/07
Page 2 of 8
ELECTRICAL DESCRIPTION
Table 4 Absolute Maximum Ratings
PARAMETER
Voltages referenced to Ground
V+ Supply Voltage
V- Supply Voltage
V+, V- Supply Slew Rate
Storage Temperature
Input Voltage
TTLIN and HI/LO Inputs
-65
Gnd – 0.3
‘V-‘ – 0.3
MIN
-0.3
MAX
+20
-20
+/-100
+150
‘V+’ + 0.3
‘V+’ + 0.3
UNITS
V
V
V/uS
°C
V
V
0.3
429OUT Outputs
Power Dissipation @ 85 °C: (> 10 Sec)
8 Lead EQ SOIC, thermal pad soldered to heat spreader land,
Junction Temperature:
Tjmax, Plastic Packages (Limited by molding compound Tg)
Tjmax, Ceramic Packages
ESD per
JEDEC A114-A Human Body Model
Lead Soldering Temperature (10 sec duration)
Notes:
1. Stresses above absolute maximum ratings may cause permanent damage to the device.
1.0
145
160
2000
280
W
°C
°C
V
°C
2. The device is tolerant of one or both outputs shorted to Ground and of both outputs shorted together.
Table 5 Recommended Operating Conditions
PARAMETER
Supply Voltage
Operating Temperature
SYMBOL
V+
V-
T
OP
CONDITIONS
9.5 to 16.5V
-9.5 to –16.5V
-55 to +85°C or
-55 to +125 °C
Plastic Package
Ceramic Packages
©2007 Device Engineering Inc
DS-MW-01070-01 Rev. J
NOT RECOMMENDED FOR NEW DESIGN – Use DEI107XA
11/26/07
Page 3 of 8
Table 6 Electrical Characteristics
Conditions:
Tcase = rated operating temperature: -55°C / +85°C or -55°C / +125°C.
V+/- = +/-9.5 to +/-16.5V Unless otherwise noted.
PARAMETER
TEST CONDITION
SYMBOL
MIN
NOM
MAX
UNITS
Input Voltage, Logic 1
Input Voltage, Logic 0
Input Current, Logic 1
Input Current, Logic 0
ARINC Output Voltage
(Differential)
One
Null
Zero
ARINC Output Voltage
(Single Ended)
Hi
Null
Lo
LOGIC INPUTS
V
IH
V
IL
VIN = 5.0V
VIN = 0.0V
I
IH
I
IL
2.0
-0.3
0
0
V+
0.8
100
-100
V
V
uA
uA
ARINC OUTPUTS
Differential Output Voltage =
429OUTA – 429OUTB.
No Load.
Referenced to Ground
No Load.
Vo
HI
Vo
null,
Vo
LO
4.5
-0.25
-5.5
5.0
0
-5.0
5.5
+0.25
-4.5
V
V
V
V
DIF1
V
DIFnull
V
DIF0
9.0
-0.5
-9.0
10.0
0
-10.0
11.0
+0.5
-11.0
V
V
V
ARINC Output Short Circuit
Current
Output Resistance:
DEI1070
DEI1071
DEI1072
Outputs shorted to Ground.
Isc
LO
Isc
HI
130
-130
37.5
10
0
1.0
2.0
mA
mA
Ohms
Ohms
Ohms
uS
Room Temperature
Rout
HI/LO = 1
No Load
Output Slew Rate
T
rise
Hi Speed
10% to 90% voltage
T
fall
amplitude of differential
output.
HI/LO = 0
Output Slew Rate
No Load
T
rise
Lo Speed
10% to 90% voltage
T
fall
amplitude of differential
output.
HI/LO = 1
Output skew time between A
Measured at 50% voltage
Tskew
and B outputs.
amplitude of both outputs.
SUPPLY CURRENT
Quiescent Operating Supply
V+ =15V, V- = -15V
Current:
HI/LO = 0 or 1
IV+
TTLIN0=TTLIN1= 0V
I
V+
IV-
No Load
I
V-
5
15
uS
200
nS
-
-14.0
6.0
-6.0
14.0
-
mA
mA
©2007 Device Engineering Inc
DS-MW-01070-01 Rev. J
NOT RECOMMENDED FOR NEW DESIGN – Use DEI107XA
11/26/07
Page 4 of 8
DESIGN CONSIDERATIONS
Transient Voltage Protection
External transient voltage suppressing devices are required to protect the device from stress such as that defined by DO160D
Section 22, Lightning Induced Transient Susceptibility. The output stage of the driver includes intrinsic clamp diodes to the
V+ and V- power rails. Consider using the 0 Ohm output option to allow use of an external 36 Ohm current limiting resistor
and transient voltage suppressor. Transients at the device must be limited to less than one diode drop beyond the power rails to
prevent excessive current to the device.
Thermal Management
Device power dissipation varies greatly as a function of data rate, load capacitance, data duty cycle, and supply voltage. Proper
thermal management is important in designs operating at the HI speed data rate (100KBS) with high capacitive loads and high
data duty cycles. Dissipation may be estimated from the graph below which shows the approximate power dissipation for
various loads and supply voltages. It is calculated for 100% data duty cycle at 100KBS with no word gap null times and must
be reduced by the appropriate data duty cycle. Adjust for the application data duty cycle using a factor of (total bits transmitted
in 10 sec period / 1,000,000) = (32 x total ARINC words transmitted in 10 sec period / 1,000,000).
Heat transfer from the IC package should be maximized. Use maximum trace width on all power and signal connections at the
IC. The exposed heat sink pad of the SOIC package should be soldered to a heat spreader land on the PCB. The pad is
electrically isolated. Maximize land size by extending beyond the IC outline if possible. Place vias on the signal/power traces
close to the IC and on the heat spreader land to maximize heat flow to the internal power planes.
429 DRIVER DEVICE POWER DISSIPATION (100kbs, 100% DC)
1.6
1.4
1.2
Power Dissipation (W)
1
100KHz, Full Load (30nF/400Ohm)
0.8
100KHz, 2/3 Load (20nF/600Ohm)
100KHz, 1/3 Load (10nF/1200Ohm)
0.6
0.4
0.2
0
7
8
9
10
11
12
13
14
15
16
Supply Voltage (+ / - V)
©2007 Device Engineering Inc
DS-MW-01070-01 Rev. J
NOT RECOMMENDED FOR NEW DESIGN – Use DEI107XA
11/26/07
Page 5 of 8
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