Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C
Package Type
24-Lead Hermetic DIP (W)
24-Lead Plastic DIP (P)
24-Lead SOL (S)
JA
1
JC
NC = NO CONNECT
Units
°C/W
°C/W
°C/W
69
62
72
10
32
24
NOTE
1
θ
JA
is specified for worst-case mounting conditions, i.e., q
JA
is specified for
device in socket for Cerdip, and P-DIP packages;
JA
is specified for device
soldered to printed circuit board for SO package.
CAUTION
1. Do not apply voltages higher than V
DD
or less than GND
potential on any terminal except V
REF
and R
FB
.
2. The digital control inputs are Zener-protected; however,
permanent damage may occur on unprotected units from
high-energy electrostatic fields. Keep units in conductive
foam at all times until ready to use.
3. Do not insert this device into powered sockets; remove
power before insertion or removal.
4. Use proper antistatic handling procedures.
5. Devices can suffer permanent damage and/or reliability deg-
radation if stressed above the limits listed under Absolute
Maximum Ratings for extended periods.
ORDERING GUIDE
Model
DAC8222EW
DAC8222GP
DAC8222BTC/883*
DAC8222FW
DAC8222FP
DAC8222FS
INL
GFSE
(LSB) (LSB)
±
1/2
±
1/2
±
1
±
1
±
1
±
1
±
1
±
2
±
4
±
4
±
4
±
4
Temperature
Range
–40°C to +85°C
0°C to +70°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package
Description
Cerdip-24
P-DIP-24
LCC-28
Cerdip-24
P-DIP-24
SOL-24
Package
Option
Q-24
N-24
E-28A
Q-24
N-24
R-24
*Consult factory for DAC8222/883 MIL-STD data sheet.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the DAC8222 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. C
–3–
DAC8222
DICE CHARACTERISTICS
11.
12.
13.
14.
15.
16.
17.
18.
19.
10.
11.
12.
AGND
I
OUT A
R
FB A
V
REF A
DGND
DB11(MSB)
DB10
DB9
DB8
DB7
DB6
DB5
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
DB4
DB3
DB2
DB1
DB0 (LSB)
DAC A/DAC
B
LDAC
WR
V
DD
V
REF B
R
FB B
I
OUT B
Substrate (die backside) is internally connected to V
DD
.
DIE SIZE 0.124
×
0.132 inch, 16,368 sq. mils
(3.15
×
3.55 mm, 10.56 sq. mm)
WAFER TEST LIMITS
(@ V
Parameter
Relative Accuracy
Differential Nonlinearity
Full Scale Gain Error
1
Output Leakage
(I
OUT A
, I
OUT B
)
Input Resistance
(V
REF A
, V
REF B
)
Input Resistance Match
Digital Input High
Digital Input Low
Digital Input Current
Supply Current
DC Supply Rejection
(∆Gain/∆V
DD
)
DD
= +5 V or +15 V, V
REF A
= V
REF B
= +10 V, V
OUT A
= V
OUT B
= 0 V; AGND = DGND = 0 V; T
A
= +25 C)
Conditions
Endpoint Linearity Error
All Grades are Guaranteed Monotonic
Digital Inputs = 1111 1111 1111
Digital Inputs = 0000 0000 0000
Pads 2 and 24
Pads 4 and 22
DAC8222G
Limit
±
1
±
1
±
4
±
50
8/15
±
1
2.4
13.5
0.8
1.5
±
1
2
0.1
0.002
Units
LSB max
LSB max
LSB max
nA max
Symbol
INL
DNL
G
FSE
I
LKG
R
REF
∆R
REF
R
REF
V
INH
V
INL
I
IN
I
DD
PSR
kΩ max
% max
V min
V min
V max
V min
µA
max
mA max
%/% max
V
DD
= +5 V
V
DD
= +15 V
V
DD
= +5 V
V
DD
= +15 V
V
IN
= 0 V or V
DD
; V
INL
or V
INH
All Digital Inputs V
INL
or V
INH
All Digital Inputs 0 V or V
DD
∆V
DD
=
±
5%
NOTES
1
Measured using internal R
FB A
and R
FB B
.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
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